Fully Differential Amplifier Provides High Voltage, Low Noise Signals for Precision Data Acquisition Signal Chain

Where R1//R2 is the parallel equivalent resistance of R1 and R2. It is also obvious from the previous discussion that the total noise of U3 and U4 is mainly composed of amplifier voltage noise and resistor noise, so it is best to keep the resistor value low to effectively reduce its contribution to the overall noise, making the amplifier noise the only major noise source. The noise at the output of the VOCM circuit will appear at the input of the differential stage, which will then be amplified by the differential stage and transmitted to the output.

VOCM Circuit—Single Amplifier U3 Noise

As mentioned earlier, the noise at the output of U3 appears as common mode to the inputs of U1 and U2 (shown as inp and inn, see Figure 11), and therefore does not contribute noise to the differential stage. The additional noise comes from resistors R3 through R8. A closer inspection shows that each input of the differential stage has three parallel resistors—R3 through R5 for the positive input and R6 through R8 for the negative input (Figure 11c), which also makes the noise contribution of the resistors very small.

Of the two circuits, the dual-amplifier and single-amplifier VOCM circuits, the latter has a much lower noise contribution, but its overall signal gain is lower. In addition, it consumes less power and requires fewer amplifiers. Equation 7 shows the noise at the output of the VOCM circuit in Figure 11; Equation 8 shows the corresponding noise contribution to U1 and U2 from changes at the output of the differential stage.

Putting it all together—total SNR of the ADC signal chain

The total SNR of the ADC signal is determined by the total noise contribution of the analog front end (AFE) and the ADC, which may include noise from other noise sources. The total SNR of the ADC signal chain is given by the following equation:

Figure 11. Single amplifier VOCM noise model.

where VREF is considered to be the positive full-scale of a bipolar output ADC.

Overall, the total SNR of the signal chain can be summarized in Figure 12.

Figure 12. Data acquisition front-end signal chain

The noise of the ADC combined with the noise at the input of the AFE will make the actual total SNR of the ADC lower than the theoretical or ideal value. In order to combine the noise of the AFE with the noise of the ADC, the SNR of the ADC needs to be converted to its rms integrated noise equivalent as follows:

For example, the ADAQ7767-1 has a typical SNR of -106 dB and an equivalent rms noise of 14.5 μV.

The ADAQ7767-1 is a 24-bit data acquisition solution with an integrated ADC driver and antialiasing filter, with gains of 1, 0.364, 0.143 V/V, and a noise bandwidth (BW) of 110 kHz at 250 kSPS, with a steep cutoff frequency determined primarily by its digital brick-wall filter. The typical broadband voltage noise of the ADA4625-1/ADA4625-2 is 3.3 nV⁄√Hz, so the output noise contribution of the differential stage (U1 and U2) in Figure 13 (noise gain of 6) is:

eN,V_U1U2 = [√2(3.3 nV)2] (500 Ω + 1.5 kΩ + 1 kΩ)/500 Ω = 28 nV⁄√Hz; due to U1 and U2 RTI noise, using Equation 1.

eN,RES_U1U2 = √[2.87 nV(6)]2 + (4 nV)2 + (4.97 nV)2 = 18.4 nV⁄√Hz due to the resistor gain network, using Equation 3.

eN,U1U2 = √(28 nV)2 + (18.4 nV)2 = 33.5 nV⁄√Hz, the total output noise contribution of the differential stage.

According to Equation 8, the parallel equivalent value of the three resistors (1 kΩ) at the input of the differential stage is 333.3 Ω, and the noise is 2.3 nV⁄√Hz:

eNO,VOCM_U3 = 6√2(2.3 nV)2 = 19.5 nV⁄√Hz, the output noise contribution due to resistors R3 to R8.

Therefore, the total output noise at the input of the ADAQ7767-1 is calculated as:

The ADAQ7767-1 input gain stage configuration is set to 0.143 V/V, with an input range of ±28 V (56 V pp). Given that the typical SNR of -106 dB is equivalent to 14.5 μv rms noise, combining the input circuit noise with the device noise yields the following:

The input circuitry contributes very little to the total system noise, in part due to the low input gain of the ADAQ7767-1. Note that the 110 kHz comes from the brick-wall digital filter, so there is no need to factor in the filter bandwidth when multiplying by the bandwidth. Based on a typical SNR of -106 dB, the final SNR of the signal chain would be:

A noise simulation (Figure 14) of the input circuit in Figure 13 using LTspice shows a total rms noise of 12.3 μV rms at a 110 kHz bandwidth. Multiplying this by the gain of 0.143 V/V gives a noise of 1.8 μV rms at the input of the ADAQ7767-1, which is the same as the calculated total input noise value.

Figure 13. ADAQ7767-1 precision signal chain with high voltage input

Figure 14. LTspice noise in the ADAQ7767-1 input circuit shown in Figure 13.

Table 1 shows the total signal chain SNR obtained when using other gains of the ADAQ7767-1.

Table 1. Total SNR of the signal chain at different gains of the ADAQ7767-1.

Only a single amplifier VOCM circuit is used in Figure 13. This circuit can be used to provide large input voltages to a front-end signal chain system without significantly affecting the noise performance. A dual amplifier VOCM circuit can provide similar noise performance at the same overall signal gain. The noise equation given in the Noise Analysis section, “VOCM Circuit—U3 and U4 Noise” can be used to calculate the total noise at the output of the dual amplifier VOCM circuit, and the same techniques and concepts can be applied to calculate the overall SNR of the signal chain.

in conclusion

Using the ADA4625-1/ADA4625-2 to create a composite FDA in the circuit described in this article enables a low noise, high voltage output solution with adjustable common mode, which can drive a high performance data acquisition signal chain with a wide input range. By properly configuring the feedback network of the differential stage, this solution can support both single-ended and differential inputs. The single amplifier VOCM circuit has an advantage over the dual amplifier VOCM circuit because it consumes less power and uses fewer amplifiers. Our example shows that the FDA circuit does not significantly affect the overall SNR of the ADAQ7767-1 signal chain at lower gains. For gains of 1 V/V, 0.364 V/V, and 0.143 V/V, the input ranges are ±4.096 V, ±11.264 V, and ±28 V, respectively; the lowest gain has the widest input range and benefits the most from this solution.

About the Author

Darwin Tolentino is currently a product/test development manager at Analog Devices, based in General Trias, Cavite, Philippines, focusing on precision μModule® signal chains, which provide integrated complete solutions for precision data conversion. He joined Analog Devices in 2000 as a product manufacturing engineer and later as a product and test development engineer, designing ATE solutions for a variety of linear and precision products such as amplifiers, voltage references, and converters.