Fully Differential BiCMOS Sample/Hold Circuit Simulation Design

0 Introduction

With the research and development of digital technology, microcomputer and analog-to-digital conversion technology, analog-to-digital converter (ADC) as an analog and digital signal interface circuit has been widely used. Since the accuracy and speed of the sample/hold (S/H) circuit, an important component of ADC, directly determine the performance of ADC, designing a high-performance S/H circuit is an important part of improving ADC performance. There are many literatures on S/H circuits. For example, literature [1] designed a charge flipping S/H circuit, but the paper did not consider the influence of the switch on-resistance on the circuit performance, and the S/H circuit had large distortion. Although the S/H circuit designed in literature [2] considered the influence of the switch on the circuit, it did not consider the influence of the common-mode output voltage of the fully differential op amp circuit on the static operating point. In order to solve the problems of large distortion and unstable static operating point of the traditional S/H circuit, a high-speed, high-precision 10-bit fully differential BiCMOS S/H circuit was designed using 0.25 μm BiCMOS process. The improved bootstrap switch circuit and dual-channel switched capacitor common-mode feedback circuit (CMFB) design in this paper are innovative.

1 Overall design concept

Figure 1 shows the structure of the s/H circuit, where Ucm is the common-mode input voltage of the op amp. The sampling switches N1 and N2 are designed as the bootstrap switches of Figure 2, and N3 to N8 use NMOS switches. The above switches are closed when the corresponding clock signal is at a high level. When φ1d is at a high level and φ2 is at a low level, the input voltage uI is sampled through the capacitor CS; when φ1d is at a low level and φ2 is at a high level, the circuit enters the holding stage, and uI is connected to the output of the op amp through the sampling capacitor CS and the feedback channel. The output load is driven by CL. Such a sampling circuit structure makes the feedback coefficient close to 1. According to the derivation, in the sampling stage, the CMOS switch operates in the linear region, and the relationship between the sampling switch gate-source voltage UGS and the input voltage uI is:

UGS=UCP-UIsin(2πfIt)(1)

Where: UI is the amplitude of the input voltage uI; fI is the input signal frequency; UCP is the amplitude of the sampling clock signal. In the hold phase, φ2 is turned on, the lower plate of CS is directly connected to the output of the op amp, and uI is transmitted to the output through the sampling capacitor; when the sampling phase transitions to the hold phase, channel charge injection occurs in the CMOS device, and a clock feedback channel appears in the hold phase due to capacitive coupling. Therefore, the lower plate sampling technology is used to reduce the impact of the switching action on the sampling signal, and the positive and negative charges stored on CS in the two phases cancel each other, thereby eliminating the error generated when the op amp is working. In addition, selecting a suitable time constant RC can increase the sampling rate.

2 Design of input gate-source bootstrap switch

When uI=UIsin(2πfIt), the on-resistance of CMOS switches N1 and N2 in Figure 1 is nonlinear with the input signal. Therefore, when sampling continuous-time signals, signal distortion and amplitude fluctuation will occur, which limits the sampling rate and the opening time of the S/H circuit. The larger the gate-source voltage of the CMOS switch, the smaller the on-resistance. If N1 and N2 are designed as gate-source bootstrap switches, it can be ensured that the gate-source voltage of N1 and N2 does not exceed VDD, then the on-resistance is close to a constant and the distortion is minimized. The designed gate-source bootstrap switch is shown in Figure 2. When CP is high, VN1 and VN2 are turned on, capacitor C3 is charged to VDD, VN8 and VN6 ​​are turned on, and VN7 is turned off. When CP is low, VN1, VN2 and VN8 are disconnected, VP4, VH5 and VN7 are turned on, and the voltage on C3 is added to VP5 through VP4, VN7 and VN5, and its gate-source voltage UGS = VDD; when CP is high, the gate-source bootstrap switches N1 and N2 are turned on, and when CP is low, the gate-source bootstrap switches N1 and N2 are turned off. When VN6 is turned on in the CP phase, the voltage at point A is high, and switches VN1 and VN2 present a resistive load. Therefore, there is a leakage current ID as shown by the dotted line in Figure 2, which seriously restricts the improvement of the op amp gain. VP6 is used for clamping, so that VN6 in the CP phase is in the off state, and the bootstrap voltage of the sampling switches N1 and N2 is increased by 10%, and the leakage current is reduced by 40%. Due to the existence of the lining effect, the on-resistance of N1 and N2 cannot be kept at a constant value. The use of a small-sized VP5 can not only reduce the on-resistance, but also improve the linearity. The output buffer capacitor C4 in Figure 2 plays an isolation role.

3 Design of Fully Differential Op Amp

For the sampling/holding circuit in Figure 1, the input differential signal is sampled at time φld, and the charge stored on Cs at the previous moment is transferred to the output end at time φ2. φ1 is the control clock signal of the lower plate sampling switches N3 and N4, which is delayed by t1 compared to the clock signal φ1d, so that switches N3 and N4 are turned on or off before switches N1 and N2. Figure 3 shows the clock signal required by the circuit in Figure 1: The designed S/H circuit is a zero-order sampling circuit, because both N7 and N8 are turned on during the sampling stage, and the input and output signals have the same DC component; the voltage change is not obvious during the sampling and holding stage, but the output voltage of the op amp must be set to 0 V in each sampling stage. Therefore, in addition to high-speed and high-precision performance, the designed fully differential op amp must also have the characteristics of short-circuiting the input and output ends.

Figure 4 is a multi-gain-stage folded common-gate-common-source op amp circuit, which uses Q1 and Q2 bipolar transistor (BJT) differential input mode, common-gate-common-source mirror current sources VP3 and VP4, VP1 and VP2 as active loads to improve the voltage gain of the op amp; Q3, Q4 and Q5, Q6 common-base-common-emitter circuits are used as the differential output stage of the op amp to enhance the load driving capability of the op amp and have high-speed characteristics; the switched capacitors form a common-mode feedback circuit (CMFB) to make the DC components of the output signal and input signal of the op amp equal; UB1, UB2, UB3 and UB4 are bias voltages. The conversion time tC and the settling time tS are approximately 1/8 and 3/8 of the sampling period TS, respectively. After calculation, when fS is 250 MHz, tC=0.5 ns, tS=1.5 ns. This requires a conversion rate (SR) of 500 V/μs, calculated as follows: SR = UP-P/tC (where UP-P is the peak-to-peak value of the input voltage, UP-P = 250 mV). In order to obtain a higher DC gain and high precision for the op amp, the absolute error of the designed S/H circuit is δ≤±ULSB/2, and its output voltage RMS value is U. The relationship between the DC gain A, sampling capacitor CS and parasitic capacitance CP is:

Uo≈UI[1-(1+CP／CS)／A](2)

It can be seen from formula (2) that by increasing the DC gain A of the op amp to reduce the gain error (1+Cp/Cs)/A, the deviation between Uo and UI can be made less than 1/2N+1 (N is the number of bits of accuracy that the system wants to obtain). Therefore, for a 10-bit system, the voltage gain is at least 67.21 dB, and CP≈0.12 pF at this time. Considering the requirement of circuit speed-up, CS=1 pF is taken. For the linear sampling circuit, in order to make tS=0.375 7TS, the unit gain bandwidth fT is taken to be greater than 725MHz. The relationship between fT and the feedback coefficient F and the settling time constant τS is as follows

fT>1/2π(FτS)=1/2π[F(tS／7.6)] (3)

Where: setup time tS = 7.6τs, F = 0.89. Compared with CMOS op amps, BiCMOS op amps not only have high gain and low noise characteristics, but also have shorter setup time ts and faster speed, especially its phase margin is greater than 45°, so the working performance of the op amp is stable.

4 Design of dual-channel common-mode feedback circuit

Because the common-mode output voltage of the fully differential folded op amp is sensitive to the adaptation of the device, adding a dual-channel switched capacitor CMFB circuit to the op amp can achieve the purpose of stabilizing its static operating point and increasing the common-mode output voltage swing. Figure 5 is a common-mode feedback circuit designed with a switched capacitor structure to stabilize the output swing and circuit impedance. The designed CMFB circuit ensures that the op amp input and output are short-circuited by feedback correction of the common-mode output voltage. In Figure 5, uO+ and uO- are the output voltages of the op amp, uc is the ideal common-mode output voltage of the op amp, uc=(uO++uO-)/2, and uc is the gate voltage of the common-gate-common-source current sources I3 and I4 formed by VP and VP in Figure 4. The common-mode feedback coefficient β=2CS/(2CS+CP), Figure 5φ1 and φ2 are clock signals, and the switches are both PMOS tubes; at φ1, the switched capacitor CS is charged, and at φ2, the non-switched capacitor Cc generates the average value of the output voltage to form the voltage that controls the op amp current source IS. The DC voltage on CC is determined by CS. CS and CC are connected in parallel between the two bias voltages UB1 and UB2 to act as a switch. UB2 = uc-VDD, and CS is 0.1 to 0.25 CC. Figure 6 shows the simulation waveform of the common-mode output voltage uc when the power supply voltage is 1.2 V, the input voltage uI peak-to-peak value is 0.6 V, and the 0.18 μm CMOS process is used. From Figure 6, it can be seen that the maximum output voltage amplitude of uc is Ucm≈600 mV, and the operational amplifier reaches the stable time of the common-mode output voltage tW=(4.135-4.12)×10-7s≈1.5 ns.

5 Experimental results and analysis

Using the simulation environment of Cadence Spectre software tool, the simulation experiment was carried out using SMIC's 0.25μm standard BiCMOS process. The parameters of the experimental op amp circuit are as follows: the input signal frequency fI is a sine wave voltage of 0 to 10 MHz, the common mode input voltage is 1.5 V, UP-P=1 V, fS=250 MHz, and the output load capacitance CL=0.5 pF. From the frequency response curve of the sampling amplifier in Figure 7, it can be seen that the op amp DC voltage gain A=72 dB, the unit gain bandwidth fT=1.6 GHz; when the feedback coefficient F=0.89 of the S/H circuit, the corresponding phase is -107.9°, so the phase margin Pm is 72.1°, which meets the system bandwidth requirement of more than 725 MHz, and the phase margin is greater than 45°, so the designed system is stable. Figure 8 shows the designed S/H circuit. The discrete Fourier transform (DFT) spectrum distribution obtained through simulation experiments shows that when fI=10 MHz, fS=250 MHz, the SFDR of the S/H circuit is -61 dB, SNR=62 dB, the third harmonic voltage 201gU3=-105.6 dB, and the SNR is greater than 50 dB. At this time, the S/H resolution ENOB=(SNR-1.76)/6.02>10 bits, which meets the performance requirements of a 10-bit ADC. Table 1 shows the simulation results of the op amp, with a settling time tS=1.37 ns, a conversion rate SR=500 V/μs, and a power consumption PD=8 mW. The shorter tS, the higher SR, and the lower PD meet the high-speed requirements of the ADC. Table 2 shows the simulation performance comparison between the designed S/H circuit and other reference S/H circuits. It can be seen from the table that the designed S/H circuit has fS=250 MHz and a moderate sampling frequency; its VDD=3 V, which is 0.3 V lower than the S/H circuit in reference [3], and its power consumption PD=10.85 mW, which is between the first two and 15.15 mW lower than the S/H circuit in reference [3]. However, it has a high precision of 10 bits, which is two levels higher than the S/H circuit in reference [3].

6 Conclusion

The S/H circuit is designed based on the fully differential folded BiCMOS operational amplifier using 0.25μm SiGe BiCMOS process. The S/H circuit designed in this paper adopts the new technology of bottom plate sampling and improved bootstrap switch, thereby improving the sampling rate and linearity. The experimental data show that the designed fully differential folded BiCMOS operational amplifier has high gain, high precision and high gain bandwidth performance. The limited number of BJTs selected in the key parts of the operational amplifier make the circuit have a faster conversion rate and large current driving capability, and the settling time of the operational amplifier is reduced; and the newly designed dual-channel common mode feedback (CMFB) circuit not only stabilizes the static operating point, but also improves the temperature stability; in addition, the sampling switches in the designed S/H circuit are uniformly set to CMOS switches, so the power consumption is greatly reduced. Since the simulation results of the S/H circuit meet the performance requirements of 10-bit precision ADC when fI=10 MHz and fS=250 MHz, this S/H circuit has a guiding role in the design of high-speed, low-voltage, low-power ADCs and other microprocessors and signal conditioning circuits.