On-Chip Calibration Advantages of New Synchronous SAR ADCs

The On-Chip Calibration Benefits of New Simultaneous SAR Analog-to-Digital Converters

On-Chip Calibration Advantages of New Synchronous SAR ADCs

summary

This article evaluates the effects of external resistors in front of a resistive analog-to-digital converter (ADC). These families of simultaneous sampling ADCs include a high input impedance resistor programmable gain amplifier (PGA) to drive the ADC and scale the input signal, allowing for direct connection of sensors. However, there are several reasons why during design, we end up adding external resistors in front of the analog inputs. The following section theoretically explains the expected gain errors as a function of the resistor size and describes several ways to minimize these errors. This article also investigates the effects of resistor tolerance and different calibration options on the ADC input impedance. In addition to the theoretical investigation, several devices are measured and compared using a bench to demonstrate the excellent accuracy achieved with the on-chip gain calibration feature. The gain calibration feature provides a systematic error of less than 0.05% for a wide range of front-end resistor values ​​without any calibration routines, only a write to a single register per channel.

Introduction

Traditionally, simultaneous sampling successive approximation register (SAR) ADCs have been seen as a response to demand, primarily from energy customers, to provide protection relay applications. In transmission and distribution networks, protection relays monitor the grid to react to any fault conditions (overvoltage or overcurrent) as quickly as possible before severe damage occurs.

To monitor the transmitted power, the current and voltage need to be measured synchronously. The current is measured through a transformer (CT), after passing through the transformer, the current is reduced, providing isolation, and converted to voltage through a load resistor. The voltage is measured through a resistor network, which is a voltage divider that reduces the voltage from the kV range to the V range. Analog Devices provides synchronous sampling ADCs to monitor voltage and current to simplify power calculations for dual, quad, or octal devices. The signal chain schematic shown in Figure 1 is typically used to measure single-phase, and power in multiphase power systems requires the use of a data acquisition system (DAS) with a higher channel count, that is, 8 channels for 3 phases and 1 neutral phase.

Figure 1. Typical signal chain in a power monitoring application. Only one phase is shown for simplicity.

When to use external front-end resistors

Although resistive input ADCs are designed to interface directly with most sensors, in some cases it may be necessary to add external resistors in front of the analog inputs. This may occur, for example, if the application requires additional anti-aliasing filtering or if the inputs need to be protected from overcurrent faults.

Anti-aliasing filter

Although resistor-input ADCs typically provide an internal antialiasing filter, many applications may run at lower sampling frequencies and, therefore, require a lower corner frequency.

A common requirement is to collect 256 samples per power frequency cycle, which means that for a 50 Hz power grid system, the sampling frequency (fS) is 12.8 kSPS.

The sampling frequency is so low that an external low-pass filter (LPF) needs to be added in front of the input of the resistor ADC to suppress frequencies above 6.4 kHz, which is the Nyquist frequency (fS/2). This can be achieved by adding a first-order RC filter.

Input protection

In other application examples, particularly in the protection relay market, excessive current may flow into the analog input pins when a fault occurs. To avoid damage to the device, the Absolute Maximum Ratings (AMR) dictate that the input current be limited to less than 10 mA. We recommend using an external series resistor to limit this potential input current.

If the sensor output voltage unexpectedly increases to ±30 V, the input clamp protection circuit (which can pass voltages up to ±16.5 V) will turn on and pass a large amount of current, damaging the device. Using a 1.35 kΩ RFILTER in front of the analog input will prevent currents above 10 mA from flowing during overstress; however, we recommend using a larger resistor (such as 10 kΩ) to prevent the frequency band from reaching its maximum limit.

Figure 2. AD7606 input clamp protection characteristics

In any case, one of the large resistors (for either antialiasing filter (AAF) or current limiting) calculated in Equation 2 must be used to ensure that both conditions are met. However, note that if the potential overstress of the analog input signal under fault conditions is less than ±21 V and an external AAF is not required, then an external resistor may not be required.

Error caused by external resistors

The downside of introducing such external resistors is that they will affect the accuracy of the system, whether they are used for additional filtering or to protect the device from large currents. For example, the AD7606 is factory-trimmed to provide very low offset and gain errors over temperature and supply ranges, 32 LSB and 6 LSB maximum, respectively. However, after adding external passive components, these specifications are no longer valid because the system gain error (which the system sees as a resistive input to the ADC + a resistor in front) increases to be greater than the gain error of the AD7606. System designers are concerned about this system gain error because it means they must perform their own system gain calibration to guarantee that their end product will meet the target accuracy required by the standard or end user. There are two methods we can use to perform system gain calibration:

►Gain calibration is performed in production, that is, each system produced is tested through a calibration procedure, the calibration coefficients are stored, and then these coefficients are used to remove the gain error. This is similar to what is performed at the IC level for ADCs, but at the system level.

► Use a fixed correction factor for each ADC sample. Because the analysis given in the next section explains the system gain error in detail, the digital host controller multiplies each sample acquired from the ADC by a factor that eliminates the system gain error. This is referred to as back-end calibration.

Using the first solution, you can achieve excellent accuracy, but it takes a long time to perform factory testing, which can significantly increase the cost of the product. The second solution, while cheaper, is not as accurate because it is based on the typical input impedance of the ADC and uses controller resources that can be limited in some cases. Sometimes, to avoid both complications, customers may choose to use a large input impedance, in which case the error caused by the front-end resistor is reduced, resulting in improved system accuracy. By using this approach, the problem is transformed from a system problem to an IC problem. However, this may not be the most effective approach because increasing the input impedance means that a new solution must be developed, which takes time and can lead to new problems, such as higher noise due to these larger on-chip resistors. The AD7606B and AD7606C have an on-chip gain calibration function that can eliminate the system gain error caused by external resistors, achieving excellent accuracy without calibration and avoiding the cost of the system solution.

Gain Error

The gain of the PGA is determined by the feedback resistors (RFB), which program the analog input range and the input impedance (RIN), which is fixed and typically 1 MΩ. These resistors are adjusted to properly set the PGA gain to scale the ±10 V or ±5 V analog input signals (AIN+/-) to the ADC input range of ±4.4 V, as shown in Figure 3.

Figure 3. AD7606 internal PGA. Only ±10 V range is used as an example

However, the gain changes (moves from the ideal value) when a series resistor (which we will call RFILTER) is added in front of the PGA. This resistor actually changes the denominator in Equation 3; therefore, the system gain will be lower than its adjusted gain.

Figure 4. Series resistors in front of the AD7606’s analog inputs (VX+ and VX-) change the system gain.

For example, if a 30 kΩ resistor is used in front of the AD7606, then a 10 V input signal will no longer be a 10 V signal when it reaches the ADC output because the PGA output of the AD7606 is no longer 4.4 V. The PGA output will be 4.2718 V, and if we plot this new theoretical system gain transfer function, we can see that the gain error is approximately –3%, as shown in Figure 5.

Figure 5. The amplitude of the PGA output decreases as RFILTER increases.

(a) shows the PGA output (unit: V), (b) shows the PGA output voltage (percentage of FS).

We can calculate the gain error (a function of RFILTER) using the following formula:

For ease of evaluation, we can graphically represent Equation 5 as the system gain error, showing the % vs. full scale (FS) and the relationship vs. RFILTER, as shown in Figure 6.

Figure 6. System gain error (% of FS) as a function of the external RFILTER resistor in the AD7606 (1 MΩ input impedance).

AD7606B/AD7606C

During the development of the AD7606B project, the input impedance and resolution of three products were specified as shown in Table 1.

Table 1. AD7606B project types, typical input impedance, and resolution

In either case, whether RIN is 5 MΩ or 1.2 MΩ, the larger the series resistance (RFILTER), the lower the system gain, that is, the larger the gain error. However, the larger the RIN, the smaller the effect of RFILTER, as shown in Equation 5. In theory, for resistors up to 50 kΩ, the system gain error is reduced from almost 5% to 1%.