Design of a high-speed digital-to-analog converter for SoC

1 Introduction

System on chip (SoC) is an important direction of integrated circuit development. Due to the many advantages of digital signal processing and the improvement of digital integrated circuit performance and the reduction of cost in recent years, the position of digital circuits in SoC systems is becoming more and more important. Since people always need to convert digital signals into corresponding physical quantities in the real world, digital-to-analog converters (DACs) have become an indispensable and important module in SoC systems. With the continuous improvement of digital signal processing speed, the demand for high-speed DACs in SoC systems has become more urgent. In many fields such as communication, measurement, automatic control, and multimedia, high-speed DACs are widely used, and their performance has an important impact on the overall performance of the system. The design of high-speed DACs is of great significance for the design of good high-performance SoC systems.

This paper selects the deep submicron CMOS process widely used in SoC chips to realize a 10-bit high-speed DAC. This DAC can be used as an IP hard core in SoC design and can be reused in system designs in various different application fields. [1]

2 Design of high-speed DAC

2.1 Structure of high-speed DAC

The design of high-speed and high-precision DACs generally adopts a current-driven structure. Taking a 10-bit current-driven DAC as an example, its structure is shown in Figure 1.

Figure 1. Block diagram of a 10-bit current-driven DAC

In a current-driven DAC, if thermometer code is used instead of binary code for switch control, the linearity and spurious-free dynamic range (SFDR) performance of the DAC can be greatly improved. However, for a current-driven DAC with a precision of 10 bits or higher, if the full thermometer code is used, the area and power consumption of the decoding circuit will be too large. Most high-precision current-driven DACs choose a segmented coding structure to balance the needs of improving DAC performance and controlling the scale of the decoding circuit. [2] The DAC design in this paper chooses a 7+3 segmented coding structure, that is, the upper 7 bits of the input signal are converted into thermometer code, and the lower 3 bits are directly used in binary code.

2.2 Design of high-speed decoder

As the speed of DAC becomes faster and faster, the speed of the thermometer code decoder often becomes the bottleneck of the DAC speed. Although the use of traditional digital circuit design methods is conducive to simplifying the decoding circuit, it is difficult to achieve high-speed decoding, especially when the decoder has a large number of bits [3]. In order to effectively design a high-speed decoder, this paper combines the decoder and the delay unit into a unified synchronous circuit. According to the design principles of synchronous circuits, the design of the high-speed decoder and the delay unit is completed using automatic synthesis and layout and routing tools.

The circuit structure of the high-speed decoder and the delay unit is shown in Figure 2. The box marked with 'D' in the figure represents a D flip-flop triggered by the clock edge. As can be seen from Figure 2, the 7-bit thermometer code decoding circuit and the 3-bit binary code delay unit are placed between the D flip-flops, so that all input-output paths can be clearly written with timing constraints, which creates the necessary conditions for the use of automatic synthesis tools. The specific design process of the high-speed decoder and delay device in this design is as follows: first, use Verilog HDL language to write RTL-level code; then write the timing constraint file, use the Design Compiler tool to complete the automatic synthesis of the decoder and delay circuit, obtain the gate-level net list, and perform gate-level post-simulation; next, use the Silicon Ensemble tool to complete the automatic layout and routing of the standard unit, and use Pearl software to perform static timing analysis during the layout and routing process; finally, use Calibre software to perform DRC and LVS checks on the final layout to verify the correctness of the layout. Through the above design method, a 7-bit decoder with a maximum decoding speed of 300MHz was realized.

Figure 2 Circuit structure of high-speed decoder and delay device

2.3 Design of switch unit

The design of switch unit has an important influence on the performance of DAC under high-speed conditions. For a high-speed DAC design, not only is the DAC required to achieve a high conversion speed, but the DAC is also required to achieve good performance under high conversion speed. Therefore, the design of switch unit plays an important role in high-speed DAC design.

Figure 3 Circuit diagram of current source unit and switch unit

The switch unit used in the DAC design of this paper is shown in Figure 3. The switch unit mainly consists of two parts: a synchronous latch and a current switch. The main function of the synchronous latch is to synchronize the switching of the current switches in each switch unit in the DAC with the clock, thereby minimizing the output spurious generated by the delay error. In addition, by adjusting the size ratio of ML3, ML4 to ML5, ML6, the synchronous latch can also adjust the cross-point potential of the switch control signal (a pair of differential signals) to ensure that a pair of switches will not be turned off at the same time, thereby reducing the resulting output burrs [4]. The synchronous latch of this paper connects the clock-controlled MOS switches ML1 and ML2 in series before ML3-ML6, thereby reducing the synchronous latch's requirements for the power supply voltage, which is conducive to the implementation of the circuit in deep submicron CMOS technology.

The current switch in the switch unit consists of MSW1-MSW4. Compared with the commonly used current switches, adding MSW3 and MSW4 can play two roles: on the one hand, they reduce the glitch voltage of the digital control signal directly fed through the Cgd of MSW1 and MSW2 to the output end; on the other hand, they reduce the influence of the output voltage change on the internal node voltage of the current source, thereby improving the SFDR performance of the DAC under high-speed conditions from two aspects.

2.4 Design of current source unit

The current source unit of this paper adopts a common source and common gate current source circuit, as shown in Figure 3. The common source and common gate current source can achieve a very high output impedance, which is not only conducive to improving the linearity of the DAC during static operation, but also has an effect on improving SFDR. The size design of the current source unit has an important impact on the performance of each DAC. In the circuit shown in Figure 3, the MCS1 tube should have enough area so that the matching accuracy between the current source units can ensure the linearity requirements of the 10-bit DAC. This paper uses the Monte Carlo method to model the current source and calculates that if the yield of the 10-bit DAC (the percentage of INL and DNL both less than 0.5LSB) is to be greater than 99%, the mismatch between the current source units must meet the following requirements:

(1)

According to formula (1) and MOS tube mismatch characteristic formula (2) [5]

(2)

The minimum size of the MCS1 tube can be calculated. In formula (2), and are inversely proportional to the area of ​​the MCS1 tube and are calculated based on the specific process data provided by the chip manufacturer.

3 Simulation results

The DAC design in this paper is implemented in the SMIC 0.18μm CMOS process and simulated using Cadence's Spectre software. The simulation results show that the maximum sampling rate of the DAC can reach 300MS/s (worst case for all corners). Under the conditions of 200MS/s sampling rate and 20.8MHz input signal (1.8V power supply voltage, TT corner), the spectrum of the DAC output signal is shown in Figure 4. It can be seen from the figure that the SFDR of the DAC can reach 66.27dB at this time, which is also close to the average result of SFDR under all corners. The SFDR of the DAC is the lowest under the SS corner, but it also exceeds 60dB.

Monte Carlo simulation shows that the percentage of INL and DNL of the DAC less than 0.5LSB is greater than 99%. The DAC has a power supply voltage of 1.8V and a maximum output voltage of 1.5Vpp (differential). The power consumption is only 22.7mW at a sampling rate of 200MS/s, and the area of ​​the IP hard core is approximately 0.55mm2.

Figure 4 DAC output spectrum at 200MS/s sampling rate and 20.8MHz input signal (TT corner)

4 Conclusion

This paper proposes a design of a high-speed and high-precision DAC for SoC, and implements the design in the form of IP hard core under deep submicron CMOS process. The design has good performance under high-speed conditions, and has low power consumption and area, which can effectively meet the application requirements of SoC system design in the fields of communication, measurement, automatic control, multimedia, etc.

The author's innovation:

By adopting the synchronous circuit design principle and the design method of automatic synthesis and layout and routing, a high-speed thermometer code decoding circuit is realized. By improving the switch unit and reasonably designing the size of the common source and common gate current source, the good linearity of the DAC and the good performance under high-speed conditions are guaranteed.