Design of Intelligent A/D and D/A Modules Based on CPCI Bus

0 Introduction

In the field of industrial control, A/D and D/A modules are often used to realize data acquisition and control functions. In actual use, there are many options for communication between A/D and D/A modules and the host. For example, RS 232, RS 422, network and other interface methods. In this design, the A/D and D/A modules communicate with the host through the CPCI bus, collect data through the A/D interface, and output analog quantity to drive the actuator after being processed by the servo control software.

Thus a closed-loop control is realized. In addition, by modifying the DSP software, the module can also realize A/D or D/A functions independently.

The A/D and D/A modules in this design have the following functions:

(1) Provide 2 16-bit A/D channels, with an input signal range of ±5 V and an accuracy requirement of less than ±16 LSB;

(2) Provide 2 16-bit D/A channels with an output signal range of ±5 V and an accuracy requirement of less than ±8 LSB, and are controlled by system reset;

(3) Using TI's DSP (TMS320VC33) as the onboard processor, the DSP is mainly used to manage A/D and D/A, run control algorithms, communicate with the host, and is controlled by system reset;

(4) DSP and host use dual-port RAM (IDT7133) to realize data exchange function.

1 Design Principle

As shown in the hardware structure diagram of Figure 1, the module uses TI's high-performance CPU device TMS320VC33 as the core. The module is connected to the CPCI bus through the PCI9052 chip, and the signal of the local bus of the PCI9052 is connected to one end of the dual-port RAM. The other end of the dual-port RAM is connected to the DSP through a level buffer.

The DSP core circuit consists of DSP chip TMS320VC33, data RAM CY7C1041VC33, and program FLASH chip SST39VF800A; the address, data, and control buses of DSP are connected to dual-port RAM, A/D chip, D/A chip, and CPLD through level buffer devices. DSP exchanges data with the host computer through the dual-port RAM chip; the initialization and read and write operations of the A/D chip are also completed by the DSP; DSP controls the D/A chip to output analog signals; the CPLD mainly implements combinational logic functions, decodes the control signal input by DSP, and then outputs it to the dual-port RAM and A/D, D/A and other functional chips for use.

Dual-port RAM chip is an important component for realizing intelligent board. Because the address space resources of DSP and host computer are allocated independently and cannot directly access each other, a data buffer is needed between them. The characteristics of dual-port RAM enable it to meet this requirement.

2 Implementation Method

2.1 Selection of main components

In this design, mature technology is adopted, common and reliable control chips are selected, and some common peripheral circuits and special circuits are combined to realize all functions. That is, PC19052 is selected as the interface chip, and the chip is used to realize the PCI bus slave interface logic.

TMS320VC33 is selected as the onboard processing chip. This chip is a high-performance DSP launched by TI that is specially used to implement floating-point operations. It has strong data processing capabilities and contains rich peripheral circuit expansion interfaces.

In order to realize the level conversion function on the module, the widely used SN74ALVC164245DL is selected as the level conversion buffer chip.

2.2 PCI9052 and dual-port RAM hardware interface implementation

As shown in Figure 2, the local bus signal connecting PCI9052 and dual-port RAM includes three parts: address, data, and control signal. The address bus width is 12 bits, and the data bus width is 16 bits, so the addressing space is 2 KB of 16-bit address space. The control signal includes read-write control signal and peripheral ready completion signal. When the dual-port RAM pulls the peripheral ready completion signal low, the host can read and write the dual-port RAM by outputting the read-write control signal.

2.3 DSP design core circuit design

DSP is the core of the whole design. The DSP core circuit consists of three parts: DSP chip, FLASH and RAM. DSP exchanges data with the processing computer through dual-port RAM.

As shown in Figure 3, the DSP core circuit design is as follows. The power supply of DSP includes core operating voltage 1.8 V and I/O voltage 3.3 V, which are provided by the on-board power supply module respectively. The clock signal is provided by an external crystal oscillator. The reset signal is provided by the CPLD. Since the I/O voltage of DSP is 3.3 V, it is necessary to perform level conversion between 3.3 and 5 V when connecting to the signal with the I/O level standard of +5 V. The interrupt signal is also connected to the CPLD through a level conversion device. The address and data buses are connected to the functional devices according to the actual design needs. The JTAG interface is connected to a standard dual-row 14-pin straight-plug connector of the module. Page0~3 signals are connected to the CPLD through a level conversion device.

2.4 Power Supply Design

The system power supplies include +5 V, 3.3 V, 1.8 V, +15 V, and -15 V.

The core voltage of the DSP chip is 1.8 V, and the I/O voltage is 3.3 V, so the board needs to provide two voltage sources, 3.3 V and 1.8 V. The D/A chip needs to provide two power supplies, +15 V and -15 V. The +5 V power supply is provided by the system, and the other power supplies are obtained by converting the +5 V power supply.

For linear voltage regulation, its characteristics are simple circuit structure, small number of components required, and large input/output voltage difference, but its fatal weakness is low efficiency and high power consumption. The characteristics of DC-DC circuit are high efficiency and flexible step-up and step-down, but the disadvantage is large interference and ripple.

Comparing the same type of voltage conversion chips from Linear Technology, National Semiconductor, and Texas Instruments, the TPS73HD318 module from Texas Instruments was selected as the 3.3 V and 1.8 V voltage conversion chip. RECOM's REC3-0515DRW was selected to complete the voltage conversion between +5 V and +15 V, -15 V. They have the characteristics of more than 90% conversion efficiency, simple peripheral circuits, smaller packaging, and ripple voltage below 2.5%.

2.5 Reset Design

As shown in Figure 4, the reset input includes two parts: RESETA output by MAX1232 and RESETB output by power chip TPS73HD318. The input of MAX1232 is manual reset signal input and watchdog feeding signal input. The manual reset signal comes from the reset button, and the watchdog feeding signal comes from the CPLD. The reset output 2 signals are used by DSP and D/A respectively.

2.6 Level conversion design

Since the interface level of DSP is 3.3 V, and the interface level of CPLD and PC19052 is 5 V, a level conversion buffer chip is needed to make the two parts compatible. As shown in Figure 5, the device has two power supplies, two direction control terminals, and two enable terminals. By connecting different voltage sources, different levels can be provided for the signal pins of the device.

2.7 A/D, D/A design

The A/D and D/A chips are connected to the address data bus of the DSP through the level buffer period, and the DSP chip is responsible for the initialization and read and write control of the A/D and D/A.

3 CPLD Logic Design

The block diagram of the CPLD on-chip logic implementation is shown in Figure 6. The CPLD mainly implements three functions: the logic interface with the DSP bus, the internal registers, and the control logic.

The interface logic with the DSP bus implements the interface with the DSP logic, allowing the DSP to access the internal registers of the CPLD. The status register is a read-only register, used to read the interrupt status, the flag bit for communicating with the dual-port RAM, and other information; the control register is a write-only register, used to control the interrupt mask and modify the communication flag bit. The combinational logic is mainly used for address decoding and read-write decoding.

4 DSP software design

DSP software development is mainly based on the integrated development environment CCS provided by TI, making full use of the powerful functions of the real-time operating system DSP/BIOS, combined with its own specific processing algorithms. Quickly build a high-efficiency software system that meets the needs. In the design, DSP initialization is necessary. This design is mainly used in real-time control systems, and the main functions of its circuit are for acquisition, calculation, and output. The program flow chart is shown in Figure 7. After power-on, the program stored in FLASH starts to run, and the DSP starts to initialize the RAM memory, CPLD internal registers, A/D registers, and D/A registers in sequence. After initialization, it starts to read the A/D input. Since the A/D conversion speed is slower than the reading speed, it is necessary to query the A/D conversion status during the reading process and wait for the A/D chip to output the conversion completion signal. The read data is written to the specified location of the dual-port RAM, and the dual-port RAM and CPLD internal flag bits are refreshed to notify the host to read the data. The A/D data is calculated, and the D/A output is controlled according to the calculation results. After waiting for the query D/A conversion to be completed, the program jumps to read A/D again.

5 Conclusion

This design was used in a servo control system to achieve system functions, and sufficient attention was paid to the stability and reliability of the system. After a long period of assessment, the system is stable and reliable.