High-speed dual-channel data acquisition system based on USB2.0 technology

In recent years, the USB interface is gradually replacing traditional computer interfaces such as RS232, EPP, etc. due to its high transmission rate and true plug-and-play. At present, many chip manufacturers have launched chips that comply with the USB protocol, such as Philips' PDIUSBD12, NS's USBN9602, etc. Among the many USB2.0 chips, Cypress's EZ-USB FX2 (CY7C68013) chip is a good choice. This paper designs a data acquisition system based on EZ-USB FX2 and MAX1195. The system complies with the USB2.0 protocol standard. By connecting it to a high-precision laser longitudinal mode analyzer for debugging, it is proved that the system has achieved its intended purpose.

2. Introduction of CY7C68013 chip and MAX1195 chip

2.1 CY7C68013 Introduction:

CY7C68013 integrates USB2.0 transceiver, serial interface engine SIE, enhanced 8051 microcontroller and a programmable peripheral interface GPIF (General Programmable Interface) on a single chip. The "quantum FIFO" (FIFO, first-in, first-out memory) feature of CY7C68013 allows data to be uploaded from peripherals to the host without any intervention from the 8051 CPU. This data transmission mode completely solves the transmission rate bottleneck problem caused by the low clock frequency of the 8051 when the USB2.0 transceiver is connected to a general 8051 microcontroller. Another outstanding advantage of the CY7C68013 chip is its "soft" configuration. Code and data can be downloaded directly to the on-chip RAM through the USB interface. This function is realized through the "ReNumerationTM" function created by Cypress. The CY7C68013 chip has four programmable bulk, interrupt, and synchronous transfer endpoints, which can be set to double-buffered, triple-buffered, and quad-buffered modes, and an 8-bit or 16-bit external data interface, which can work in GPIF or SLAVEFIFO mode as needed. Among them, GPIF can achieve "glueless" connection with most parallel interfaces such as FIFO, that is, no external microcontroller or CPLD, FPGA, etc. is required. The design of this article adopts the GPIF method.

2.2 MAX1195 Introduction:

MAX1195 is a low-power, dual-channel, high-speed, eight-bit analog-to-digital conversion chip launched by MAXIM. It adopts a pipeline structure, with a maximum sampling rate of 40Mbps. It integrates two ADCs internally, truly realizing two-way synchronous sampling and conversion. Its operating voltage range is 2.7V-3.6V, with sleep mode and shutdown mode to reduce power consumption, single-ended or differential input mode, on-chip sample-and-hold (T/H) circuit, internal or external reference voltage, and user-selectable data output format: two's complement format or compensated binary format, with output enable control, which can set the output to high impedance state. In addition, MAXIM also provides 10-bit, higher sampling rate analog-to-digital conversion chips that are fully compatible with the MAX1195 pins and packages, such as MAX1197, MAX1198, etc., so system upgrades are very convenient. In this paper, internal reference voltage, dual-channel single-ended analog input, and compensated binary output format are used.

3. Introduction to the overall system structure and its working principle:

3.1 System composition:

The overall block diagram of the system is shown in Figure 1. The entire system mainly consists of the USB transmission chip CY7C68013, the first-in-first-out memory (FIFO) SN74V235 and the analog-to-digital conversion chip MAX1195. The inverter 74LVC04 mainly plays the role of logic control between MAX1195 and FIFO.

Figure 1 System overall block diagram

3.2 System working principle:

The two input signals of MAX1195 are sampled at the same time. The 16-bit data output bus allows the two data to be output simultaneously, each occupying eight bits, namely: D0A~D7A and D0B~D7B; the input of SN74V235 is 18 bits. According to the requirements of CMOS technology, the unused D16 and D17 pins are grounded. The data collected by MAX1195 is first sent to FIFO. The write clock (WCLK) of FIFO and the conversion clock of AD are inverted, which can fully meet the establishment time of MAX1195 output data and avoid data loss or repeated data writing. The (Programmable Almost Full) signal of SN74V235 is inverted by 74LVC04 and then connected to the Sleep and pins of MAX1195 to avoid FIFO overflow and data loss. The data output pins Q0~Q15 of SN74V235 are connected to the data line FD[15:0] in the GPIF mode of CY7C68013, that is, the 16-bit data bus composed of port B and port D. The timing process of data from SN74V235 to EZ-USB FX2 is controlled by the GPIF of CY7C68013. FX2 adopts the "quantum FIFO" structure. In FX2, data can be divided into two domains: USB domain and GPIF interface domain. These two domains are independent, allowing different clocks and logic to control data transmission. The USB domain is controlled by SIE, which receives or sends endpoint FIFO data through the USB port. FX2's "quantum FIFO" can transfer data between these two data domains in almost no time because the FIFO used by these two domains is physically the same. Therefore, according to the "quantum FIFO" principle, the data actually already exists in the endpoint FIFO belonging to the USB domain. The USB BULK transmission method is adopted so that the data is completely free from the intervention of the low-frequency CPU. Instead, the AutoIn mode provided by FX2 is adopted, that is, once the data in the FX2 endpoint buffer reaches the specified number of bytes, the data will be automatically packaged and uploaded from the USB port to the host.

3.3 GPIF waveform and program introduction:

GPIF is the on-chip controller of FX2's endpoint FIFO, which can completely replace the off-chip controller to achieve a "glueless" connection between FX2 and peripheral FIFO. The core of GPIF is a programmable state machine that can generate six "control" (CTL) and nine "address" (GPIFADR[8:0]) signals, receive six external (RDY) "ready" inputs, eight-bit or sixteen-bit data buses, and the clock can use FX2's IFCLK or be provided by the periphery. The detailed hardware connection of the GPIF interface in this article is shown in Figure 2.

Figure 2 Detailed connection diagram of GPIF and SN74V235

The GPIF state machine can define four waveform descriptors, which are generally: FIFO read, FIFO write, single word/byte read, single word/byte write. Cypress provides a graphical waveform description tool called GPIF Designer. Users only need to provide the GPIF waveform, and GPIF Designer will automatically generate the C language waveform code Gpif.c, which can be directly linked to the user's firmware program. The FIFORd descriptor is used in this article, and the waveform is shown in Figure 3.

Figure 3 FIFORd waveform designed by GPIF Designer

4. System software writing

The system software mainly includes three parts: firmware of the lower computer CY7C68013, USB driver and host application of the upper computer.

4.1 Firmware Programming

For firmware writing of the lower computer CY7C68013, Cypress provides a firmware program framework under Keil C51. The firmware framework completes the initialization of EZ-USB FX2, USB standard device request processing, power management services in USB suspend mode, and USB interrupt processing. Cypress also provides function hooks to speed up the addition of user code. Users only need to simply provide a USB descriptor table and code to execute peripheral functions.

4.2 Driver Programming

The USB driver under Windows system includes three layers, from high to low: USB Client Device Driver, USB Hub (Bus) Driver, Host Controller Driver. The latter two are provided by Windows system, and users only need to develop USB client device drivers. Cypress provides a general purpose driver, ezusb.sys, which can generally meet the needs of FX2 developers. This article uses Cypress's general purpose driver ezusb.sys. In order to use ezusb.sys, users must write the corresponding inf file, which binds a specific USB device to the corresponding driver. The inf file is written with reference to ezusbw2k.inf.

4.3 Host Application Programming

The general driver GPD, ezusb.sys, provides a user-mode interface for basic USB device requests and data transfers. User-mode applications send requests to the device driver through the Win32 function DeviceIoControl(). Ezusb.sys provides a series of IOCTL functions such as basic device requests, batch read and write, and synchronous read and write. Here we take IOCTL_EZUSB_BULK_READ (EZUSB bulk transfer) as an example to introduce it.

The key code for reading the endpoint FIFO of FX2 in bulk transfer mode is as follows:

DWORD ioctl_val=IOCTL_EZUSB_BULK_READ; //Set to read data from the device

Bresult = DeviceIoControl (hDevice, ioctl_val, // read data from the device

&bulkControl, //Endpoint number

sizeof ( BULK_TRANSFER_CONTROL ), // size of the incoming parameter

buffer, //buffer for reading data

length , // length of read data

(unsigned long *)&nBytes, //actual length of the data returned by the driver

NULL);

Due to limited space, other program codes are omitted.

6. Conclusion

The innovation of this paper is to give full play to the advantages of CY7C68013, and use the internal programmable state machine GPIF of FX2 to achieve "glueless" connection with the peripheral FIFO, avoiding the trouble of using peripheral ASIC or CPLD, FPGA, etc., and facilitating system upgrade. The whole circuit structure is compact, occupies a small area, and is easy to carry.

This paper uses Cypress's USB2.0 chip CY7C68013 to design a universal high-speed dual-channel synchronous data acquisition system. By connecting it with a high-precision laser longitudinal mode analyzer for testing, it is proved that the system achieves high-speed real-time data transmission and achieves the pre-designed goal. With the further popularization of USB ports and the development of computers, the USB data acquisition system designed in this paper will surely be more widely used.