IBIS Modeling - Part 1: Why IBIS Modeling is Critical to Design Success

IBIS Modeling—Part 1: Why IBIS Modeling Is Critical to the Success of Your Design

IBIS Modeling - Part 1: Why IBIS Modeling is Critical to Design Success

What is an IBIS model?

IBIS stands for Input/Output Buffer Information Specification, which represents the characteristics or behavior of the digital pins of a device that IC vendors provide to customers for high-speed design simulation. These models mimic the I/O behavior of the device using parameters specified by the IBIS Open Forum, an industry organization responsible for managing and updating IBIS model specifications and standards. IBIS models use an ASCII text file format and provide tabular voltage-current and voltage-time information. They do not contain proprietary data because the IC schematic design information such as transistor size, device model parameters and circuits used in the buffer schematic design are not disclosed in the model. In addition, IBIS models are supported by most EDA vendors and can be run on most industry-level platforms.

Why Use IBIS Models?

Imagine an IC passes testing. Then, a board is designed using that IC and immediately approved for manufacturing. Once the board is manufactured, it is discovered that its performance is substandard due to some signal integrity issues that result in crosstalk, signal overshoot/undershoot, or reflections caused by mismatched impedances. What do you think happens next? Of course, the board must be redesigned and remanufactured. At this point, time and cost are added. All of this happens because one important phase is not performed: pre-simulation. In this phase, system designers use simulation models to verify the signal integrity of the design before designing the board. Simulation models such as SPICE and IBIS have been widely developed for use in simulations, helping system designers to foresee signal integrity issues in the pre-simulation phase so that they can be resolved before manufacturing. This phase helps reduce the chances of board failures during testing.

history

In the 1990s, as personal computers became more popular, Intel® began developing a new I/O bus for its low-power ASICs that operated at about 33 MHz. To ensure that signal integrity was not compromised, IBIS was born. A team led by Donald Telian came up with an idea to create an information table for the I/O buffers and use this information to test Intel's boards. Soon, Intel shared these information tables with its customers to help them with board design, but without providing any proprietary information. In order to be able to reliably transfer the information from the paper table to the customer's simulator, Intel decided to work with EDA vendors and other computer manufacturers. They created the IBIS Open Forum to help standardize the buffer information in a computer-readable format. IBIS was originally called the Intel Buffer Information Table and was later changed to the I/O Buffer Information Specification. IBIS version 1.0 was released in 1993. Since then, the IBIS Open Forum has continued to promote IBIS, provide tools and documentation, and improve the standard to add capabilities in specialized fields. In 2019, IBIS version 7.0 was approved. This shows that IBIS continues to evolve to meet new technical requirements.

How to generate an IBIS model?

IBIS models generally simulate the behavior of the device's receiver and driver buffers without revealing proprietary process information. To do this, it is necessary to extract the behavior of the standard IBIS buffer components and represent it through VI and Vt data in tabular form.

To generate an IBIS model, data collection is usually the first step in the development process. Figure 1 shows the three main stages of generating an IBIS model.

Figure 1. IBIS model generation process

data collection

There are two ways to collect data for IBIS models:

►Simulation method

This method requires access to the device’s design schematics, datasheet, and lumped RLC package parasitics.

►Benchmark measurement method

This method requires the actual device and/or evaluation board, data sheet, and lumped RLC package parasitics.

Figure 2 is a diagram of the four major elements/components described by the IBIS model.

Figure 2. IBIS model keyword diagram

连接到引脚的两个二极管负责在输入超过工作范围或缓冲器限值时保护缓冲器。根据设计工作方式，缓冲器限值可以是功率箝位基准值，通常为VDD，或是地箝位基准值，通常为地或-VDD。这些二极管用作ESD箝位保护，在需要时导通，而上拉和下拉元件负责高电平和低电平状态期间的缓冲器驱动行为。因此，上拉和下拉数据是在缓冲器处于工作模式时获得。

In the model, these four main elements are represented in the form of voltage-current (VI) data, listed under the keywords [Power Clamp], [GND Clamp], [Pullup], and [Pulldown]. The switching behavior of the I/O buffer is also represented in the model in the form of voltage-time (Vt).

Voltage-Current Behavior Keywords

► [Power Clamp]表示数字I/O引脚的功率箝位ESD保护二极管在高阻抗状态期间的V-I行为，其相对于功率箝位基准电压。

► [GND Clamp]表示数字I/O引脚的地箝位ESD保护二极管在高阻抗状态期间的V-I行为，其相对于地箝位基准电压。

► [Pullup] indicates the VI behavior when the pull-up element of the I/O buffer drives high, relative to the pull-up reference voltage.

► [Pulldown] indicates the VI behavior when the pull-down element of the I/O buffer drives low, relative to the pull-down reference voltage.

The data for these keywords are obtained within the recommended voltage range of -VDD to 2×VDD and at three different corners (typical, minimum, and maximum). The typical corner represents the behavior of the buffer when it is operated at the nominal voltage, nominal process, and nominal temperature. The minimum corner represents the behavior of the buffer when it is operated at the minimum voltage, the worst process, and the highest operating junction temperature (CMOS)/lowest operating junction temperature (BJT). The maximum corner represents the behavior of the buffer when it is operated at the maximum voltage, the best process, and the lowest operating junction temperature (CMOS)/highest operating junction temperature (BJT).

For each voltage swept across the pin, its corresponding current is measured, thereby obtaining the voltage-current behavior required to model the buffer according to the IBIS specification. Figure 3 shows an example of the waveforms of these four VI curves obtained in the three corners.

图3.V-I曲线的波形示例：(a) 电源箝位数据，(b) 接地箝位数据，(c) 上拉数据，(d) 下拉数据。

Switching Behavior

In addition to the VI data, the Vt datasheet also includes the I/O buffer switching behavior in the form of rising (low to high output transition) and falling (high to low output transition) waveforms. This data is measured at the output connection. The load used is usually 50Ω, representing a typical transmission line characteristic impedance. In addition, it is still best to use the load that the output buffer actually drives. This load is related to the transmission line impedance used in the system. For example, if the system will use a 75Ω trace or transmission line, the recommended load used to obtain the Vt data is 75Ω.

For standard push-pull CMOS, four categories of Vt data are recommended to be included in the IBIS model:

►Rising waveform, load based on VDD

►Rising waveform, load is referenced to ground

► Falling waveform, load is based on VDD

► Falling waveform, load is referenced to ground

The two rising waveforms are included under the model keyword [Rising Waveform]. It describes the low-to-high output transition of the I/O buffer when the load is connected to VDD and ground respectively. On the other hand, the two falling waveforms under the model keyword [Falling Waveform] describe the high-to-low transition of the I/O buffer when the load is also connected to VDD and ground respectively. It should be noted that the output swing does not fully transition due to the load connected to the output. Like the voltage-current behavior, the voltage-time data is also obtained at three different corners. Examples of these transitions are shown in Figure 4.

While obtaining the Vt table, extract the ramp rate value. The ramp rate is the rate at which the voltage switches from one state to another, taken from 20% to 80% of the rising or falling transition edge. In the IBIS model, the ramp rate is listed under the [Ramp] keyword as a dV/dt ratio, usually displayed after the Vt table. This value does not include the effects of package parasitics, as it only represents the rise time and fall time characteristics of the internal output buffer.

The IBIS model also includes some data sheet specifications, based on which the simulation is performed, such as operating voltage and temperature range, input logic voltage threshold, timing test load value, buffer capacitance and pin configuration. The model also includes lumped RLC package parasitics, which are not found in the data sheet but are very important for routing simulation of high-speed design systems because these parasitics will load the simulation and affect the integrity of the signal passing through the transmission line.

Figure 4. Example waveforms of I/O buffer switching behavior: (a) rising waveform, load referenced to VDD,

(b) Rising waveform, the load is referenced to ground, (c) Falling waveform, the load is referenced to VDD, (d) Falling waveform, the load is referenced to ground.

IBIS Formatting

This section describes the second phase, building the model, also known as IBIS formatting. After gathering all the necessary data, the model can now be created. An IBIS model consists of three main parts: the main header file, the component description, and the buffer model.

The main header file contains general information about the model. It specifies the following:

► IBIS Version

Model Keywords: [IBIS Ver]

This is the version that the model is based on. It tells the simulator's parser checker what kind of data will appear in the file; therefore, it plays an important role in determining whether the model will pass the parser check.

► File name

Model Keywords: [File Name]

The actual name of the file should be in lowercase and use the correct file extension, .ibs.

► Version number

Model Keywords: [File Rev]

Helps track revisions of documents.

►Date ​

Model Keywords: [Date]