How to Design with Capacitive Digital Isolators

Today, safety regulations regarding the use and design of electronic equipment have made galvanic isolators a necessity in almost all data acquisition and transmission systems. One way to protect control system low-voltage circuits from potential high-voltage damage to sensor and actuator components in the electric field is to use digital isolators.

The purpose of this article is to tell you how to simplify the design of isolation systems. In addition to describing the basic functions of capacitive digital isolators and detailing how to install isolators in the signal path, the article also provides some valuable references for successful circuit board design.

Basic Functionality of Capacitive Digital Isolators

Figure 1 shows a simplified block diagram of a capacitive digital isolator consisting of a high-speed signal path and a low-speed signal path. The high-speed path (blue) transmits signals from 100kbps to 150Mbps, while the low-speed path (orange) transmits signals below 100kbps to dc.

Figure 1 Simplified block diagram of a capacitive digital isolator

The high-speed signal processed in the path shown in blue is divided into multiple fast transient pulse groups by the capacitive isolation barrier. The subsequent flip-flop (FF) converts these transient pulse groups into pulses with the same waveform and phase as the input signal. The internal watchdog (WD) checks the periodicity of the high-speed signal edges. In the case of a low-frequency input signal, the duration between consecutive signal edges exceeds the watchdog window. This forces the watchdog to change the output switch position from the high-speed path (position 1) to the low-speed path (position 2).

The low-speed path has several more functional components than the high-speed path. Because the low-frequency input signal requires an isolation barrier that prohibits the use of large capacitors, the input signal is used to pulse-width modulate (PWM) the carrier frequency of the internal oscillator (OSC). This creates a very high frequency that can pass through the capacitive barrier. Since the input is modulated, a low-pass filter (LPF) must be used to remove the high-frequency carrier before the actual data is transmitted to the output.

Where to Install in the Signal Chain

Digital isolators are classified into single-channel, dual-channel, triple-channel and quad-channel devices, which can realize unidirectional and bidirectional operation. Their common characteristics are as follows:

- does not conform to any specific interface standard;

- Use 3V/5V logic switching technology

- Designed for galvanically isolating digital, single-ended (SE) data lines

While the last point may seem like a design limitation, Figure 2 shows how to isolate a variety of interfaces, including low-voltage SPI, high-voltage RS232, differential USB, and differential CAN/RS485.

Figure 2: Digital isolators must be installed in the single-ended portion of the isolation interface.

One thing that all interfaces have in common is that the digital isolator must be installed in the single-ended 3V/5V portion of the isolation interface.

Since digital isolators have 1 to 2ns rise and fall times, they are prone to signal reflections in the case of long signal traces whose characteristic impedance does not match the source impedance of the isolator output. Therefore, we recommend installing an isolator close to its corresponding data receiving device and data source (for example: controller, driver, receiver, transceiver, etc.). If this is not possible in the design, then controlled impedance transmission lines must be used.

PCB Design Guidelines

For digital circuit boards, standard FR-4 epoxy glass is used as the PCB material because it not only meets UL94-V0 requirements, but also has less high-frequency dielectric loss, lower moisture absorption, greater strength/hardness, and higher flame retardancy than those cheaper materials.

To achieve low electromagnetic interference (EMI) PCB design, here is a design example with at least four layers (see Figure 3), which are: high-speed signal layer, ground layer, power layer and low-frequency signal layer from top to bottom.

Figure 3 Recommended four-layer board stackup

Routing high-speed traces on the top layer provides a clear connection between the isolator and its corresponding driver. Keep high-speed traces short and avoid using vias to ensure the lowest high-speed trace inductance.

A balanced ground plane is placed next to the high-speed signal layer to ensure strong electrical coupling between the ground plane and the signal traces. This creates a controlled impedance for the transmission line interconnects and also greatly reduces EMI. Finally, the balanced ground plane provides a very good low-inductance path for return current.

Place the power plane below the ground plane. The two reference planes form an additional high-frequency bypass capacitor of approximately 100pF/in2. Route low-speed control signals on the bottom layer. These signal links have enough margin to withstand the interruptions caused by vias, allowing greater flexibility.

A controlled impedance transmission line is a line whose characteristic impedance Z0 is always controlled by its geometric characteristics. When the line length is greater than 15mm (tr=1ns) and 30mm (tr=2ns), the line impedance must be matched with the isolator output impedance Z0~rO (as shown in Figure 4) to minimize signal reflections. This is called source impedance matching.

Figure 4 Source impedance matching: Z0 ~ rO

The dynamic output impedance, r0, of the isolator can be obtained by approximating the linear portion of the voltage-current output characteristic listed in the isolator data sheet. Generally speaking, the standard output impedance is about 70Ω. Therefore, for a standard 2-ounce copper-plated trace and FR-4 with a dielectric of 4.5, an 8mm wide and 10mm long trace geometry on the ground plane will produce the required 70Ω characteristic impedance.

Wiring Guidelines

It is recommended to follow several key layout guidelines to maintain signal integrity and low EMI.

To reduce crosstalk to less than 10%, keep the signal trace three times the distance from the high-speed signal layer to the ground layer (d = 3h). The return current density under the signal trace follows the 1/[1+(d/h)2] function, so its density will be very low at the point d>3h, thus avoiding large crosstalk in adjacent traces (see Figure 5).

Figure 5 Using d = 3h to minimize crosstalk

Using 45o trace bends (or chamfered bends) instead of 90o bends can maintain effective trace impedance and avoid signal reflections.

To achieve operation in a noisy environment, connect the idle enable input of the isolator to a suitable reference plane through a resistor (1kΩ to 10kΩ). Connect the active-high, high-enable input to the power plane, and the active-low input to the ground plane.

Avoid layer changes with fast signal traces as via inductance increases signal path inductance.

Use short trace lengths between the isolator and surrounding circuits to avoid noise introduction. Digital isolators are often accompanied by an isolated DC/DC converter, which provides power across the isolation barrier. Since the single-ended transmission signal of the isolator is too sensitive to noise introduction, the switching noise of the adjacent DC/DC converter can be easily introduced by the long signal traces.

Place bulk capacitors (such as 10μF) close to the power supply, such as a voltage regulator, or where the power enters the PCB.

Install a small 0.1μF or 0.01μF bypass capacitor on the device by connecting the power terminal of the capacitor directly to the power terminal of the device and then connecting it to the Vcc plane through vias. Connect the ground terminal of the capacitor to the ground plane through several vias (see Figure 6).

Figure 6 Connect bypass capacitors directly to the Vcc terminal

Use multiple vias for bypass capacitors and other protection devices (such as transient voltage suppressors and Zener diodes) to minimize the via inductance of the ground connection.

Summarize

Although there is a lot of information about PCB design, this article mainly provides some suggestions on digital isolator circuit board design. Following these suggestions will help complete a circuit board design that meets EMC standards in the shortest time.