Inverting Sample-and-Hold Amplifier Requires No External Resistors

Many applications require a sampling circuit whose output is opposite to the sampling point of its input signal. A simple solution is to connect a common non-inverting sample-and-hold amplifier in series with an inverting amplifier. A typical inverting amplifier is an operational amplifier that gets voltage feedback from two resistors. The values ​​of these resistors are usually equal, and they should be high enough to reduce the total power loss P=2V2/R, which is proportional to the square of the output voltage. The values ​​of these resistors should also be as low as possible to maintain the bandwidth of the operational amplifier.

Any parasitic capacitance in parallel with the feedback resistor R2 (C2 in the equation below) acts as a stage in the transfer function of the inverter. This stage results in an additional gain-frequency breakdown characteristic of the inverting amplifier, with a breakdown frequency of f2 = (1/2p) × (1/R2C2). To maintain the widest possible bandwidth, f2>fT should be used, where fT is the switching frequency of the op amp, in other words, at this frequency, the open-loop gain of the op amp drops to 1.

The Analog Devices AD8592 dual op amp has a high-quality disconnect feature that allows a different approach (Reference 1). The inverting sample-and-hold circuit in Figure 1 does not have any external resistors. Therefore, no energy is consumed in external passive devices during the hold state of the circuit. All op amps act as voltage followers. In the hold state, voltage followers B1 and A2 are enabled so that the B pin of capacitor C1 and IC2 pin 1 are grounded through the output of A2; the input voltage VIN goes to the A pin of C1 and IC2 pin 9. When a sample command is received, Q is high, and the A pin of C1 is grounded through the output of voltage follower A1. This condition causes a negative voltage -VS to appear at the input of voltage follower B2, which charges capacitor C2 to -VS at the start of the sample command. Voltage follower A3 acts as an impedance converter.

The AD8592 data sheet does not specify leakage current at the voltage follower output, but it can be assumed to be less than 10 pA. Therefore, capacitors C1 and C2 can have very small values, and the high output current of the op amp, 250 mA, can further quickly charge capacitors C1 and C2.

Voltage follower B3 acts as a delay line with an AND gate and a NOR gate to generate two semi-complementary logic control signals (Figure 2). The two signals QS and QD are held at a low level for a long time before going to an active high level (providing break-before-make operation). The input voltage is tracked by the QD high level at capacitor C1, and the last value of the voltage at the high-to-low transition of QD is a sample. At the instant of the QS low-to-high transition, the sample appears at capacitor C2 and subsequently at the output along with a negative signal.