High-speed 12-bit analog-to-digital converter and its application in image acquisition

1 Features and functions of AD7892

AD7892 is a 12-bit high-speed ADC with a successive approximation and sampling and holding function produced by ANALOG DEVICE, USA. It can be divided into three types, AD7892-1, AD7892-2, and AD7892-3, according to the different input analog signal ranges. Among them, the input signal range of AD7892-1 is ±10V or ±5V (settable), the input signal range of AD7892-2 is 0～＋2.5V, and the sampling conversion rate of these two types is 500kSPS. The input signal range of AD7892-3 is ±2.5V, and the sampling conversion rate is 600kSPS. The input signal overvoltage protection voltage of AD7892-1 and AD7892-3 is ±17V and ±7V respectively.

The AD7892 analog-to-digital converter has the following features:

●Single power supply operation (+5V);

●Built-in sample-and-hold amplifier;

●With high-speed serial and parallel interface.

The internal block diagram of AD7892 is shown in Figure 1. It contains analog signal conversion circuit, sampling and holding circuit, reference power supply (+2.5V) for A/D conversion, clock circuit, 12-bit successive approximation ADC circuit and control circuit. The conversion result can be output in parallel or serially, which is very easy to interface with microprocessor or DSP (digital signal processor). AD7892 has two packages, one is 24-pin dual in-line DIP package, and the other is surface-mounted SOIC package. The pin arrangement of AD7892 is shown in Figure 2. The function description of each pin is listed in Table 1.

2 Working sequence and converted binary code

The following is an introduction using industrial products with a temperature range of -40°C to +85°C (i.e., Class A and B) as an example. Some parameters of products with a temperature range of -55°C to +125°C (i.e., Class C) are slightly different.

2.1 Parallel Output Timing

When the MODE pin is connected to a high level, AD7892 is in parallel output mode, and its timing is shown in Figure 3. The CONVST signal t1 should be greater than 35ns. On the rising edge, the sample and hold enters the holding state and starts the A/D conversion. The conversion time tCONV is 1.47μs (AD7892-3) or 1.6μs (AD7892-1, AD7892-2). After the conversion is completed, the EOC pin outputs a negative pulse of t2≥60ns for interruption or data latching, and starts the next sampling at the falling edge of EOC. The next sampling starts as soon as the conversion is completed. The sampling time tACQ should be greater than or equal to 200ns (AD7892-3) or 400ns (AD7892-1, AD7892-2). When the conversion is completed (the falling edge of EOC), as long as CS and RD are valid, the converted 12-bit data can be obtained on DB0~DB11 after t6=40ns. CS is the same as the general chip select and can be always valid. The time t5 of the additional RD should also be greater than 35ns. The next sampling and this output can be performed simultaneously, so the minimum single sampling conversion output time is 1.47+0.2=1.67μs (600kSPS) for AD7892-3, and 1.6+0.4=2μs (i.e. 500kSPS) for AD7892-1 and AD7892-2. In Figure 3, t9≥200ns, t7≈5ns, and t3, t4, and t8 can be zero (at this time t9=tACQ).

2.2 Serial Output Timing

When the MODE pin is low, it is serial mode, and the timing is shown in Figure 4. This method can be connected to industrial standard microprocessors, controllers, and DSPs. Its conversion start signal CONVST, end signal EOC, and chip select CS are the same as Figure 3. Data should be read from the falling edge of EOC to the next sampling, that is, 200ns (AD7892-3) or 400ns (AD7892-1, -2) before the rise of CONVST. The falling edge of EOC can generate an interrupt or an RFS signal. During the readout period, RFS should remain at a low level, otherwise the data line is tri-state. SCLK is generally provided by the data receiver. The highest frequency for synchronous input and output is 20MHz (the minimum time for high and low levels is 25ns). After a delay of a period of time on the rising edge of each SCLK (minimum 5ns, maximum 25ns), one bit is output on the data line, and a total of 16 bits of data are output. The first four bits are 0, and the last 12 bits are valid data after conversion, with the high bit first and DB0 being the last bit. After the 16 bits of data are output, the output becomes a high-impedance state by the rising edge of RFS or the 17th SCLK (whichever comes first, which works). At least 16 pulses are required to read out the data. Assuming that the highest frequency of SCLK is 20MHz, the readout time is at least 800ns. Adding the sampling and conversion time, the maximum speed for AD7892-3 is 400kSPS, and the maximum speed for AD7892-1 and -2 is 357kSPS.

2.3 Converted binary code

Since the three types of analog input ranges are different, the binary codes of their conversion outputs are also different. Table 2 lists the input and output codes of AD7892-1 and AD7892-3, and Table 3 lists the codes of AD7892-2.

For AD7892-1 and AD7892-3, FSR is the full scale range. If the input is ±10V, then FSR=20V, if the input is ±5V, then FSR=10V, if the input is ±2.5V, then FSR="5V". The analog signal changes from -FSR/2→GND→+FSR/2, and the output changes from 100…000→111…111→000…000→011…111. For AD7892-2, when the input changes from 0→+2.5V, the output changes from all 0s to all 1s.

3 Application of AD7892 in CCD Image Acquisition

Figure 5 shows the circuit diagram of AD7892 used in CCD image acquisition system. The purpose is to convert the analog signal (unipolar) read out by CCD into a 12-bit digital signal so that the microcomputer can process it. The circuit adopts the parallel output mode of AD7892AN-1, and its speed is designed to be 400kSPS.

In this application, IN2 is connected to IN1, and its input range is ±5V. After the output signal generated by CCD is processed by the conditioning circuit, its output voltage range is -5V to 0V, so the output D11 to D0 is 100…000~111…111, that is, from 2048 to 4095. After D11 is inverted, the data latched by the latch is 000…000→011…111, that is, from 0 to 2047. When the microcomputer sends the CONVST signal to start the conversion, the lower eight bits of the result of the last conversion are taken away, and then the upper four bits are taken away.