Software Implementation of High Resolution Digital Potentiometer X9241

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introduction

Compared with mechanical potentiometers, digital potentiometers have many advantages. However, in some applications, the resolution of digital potentiometers often does not meet the design requirements, and the maximum number of taps is usually 1 024. Taking X9241 as an example, it includes an I2C interface and four 64-tap digital potentiometers, which can be used independently or in series. If used in the conventional way, its resolution is low. Even if four potentiometers are connected in series, it can only reach 256 taps. This paper proposes a method combining software and hardware, which can make the number of intermediate taps of the potentiometer reach 8 001 and the resolution reach 0.008%.

1 Design Principle

1.1 Basic principles

The high-resolution digital potentiometer POT is composed of 4 potentiometers, as shown in Figure 1. The 4 digital potentiometers POT0, POT1, POT2, and POT3 are all 64-tap digital potentiometers. The fixed ends of POTO and POT3 are connected in parallel, and the sliding ends are connected to the fixed end of POT12 respectively. POT12 is a 127-tap potentiometer composed of POT1 and POT2 in series. The resistance values ​​of the 4 independent potentiometers are equal and can be selected as needed. The fixed ends of the high-resolution digital potentiometer are VH and VL, and the sliding end is VW. VW is connected in parallel by the two sliding ends of POT1 and POT2.

The high resolution digital potentiometer POT consists of 4 potentiometers

Assume that the sliding end positions of POT0, POT1, POT2, POT3, and POT12 are x0, x1, x2, x3, and y respectively, and the sliding end position of POT is z.

The following control strategies are currently adopted:

① If the sliding end position of POT3 is x, the sliding end position of POTO is synchronously adjusted to x+1, that is, the two potentiometers always maintain an interval of 1, which is equivalent to coarse adjustment;

② Adjusting the sliding end position y of POTl2 is equivalent to subdividing the interval of 1 into several equal parts, that is, fine adjustment.

By using the equal calibration circuit method, the relationship between z and x and y can be obtained.

Assume that the potentials of VL and VH terminals are 0 and U respectively, and the potential of the sliding terminal is UW. According to the electrical formula, we can get:

formula

Among them, U0W and U1W are the output potentials of POT1 and POT1 sliding terminals respectively, and are added to the two fixed terminals of POT12.

Formula (3) is derived from formula (1) and formula (2), and the output potential of the VW terminal is obtained.

formula

That is, the resistance of the sliding end of the potentiometer POT relative to VL is:

formula

If the step increment of z is set to 1, then:

formula

Among them, R is the resistance of the fixed end of the potentiometer, the value range of x is 0 to 62, the value range of y is 0 to 127, the value range of z is 0 to 8 001. The resolution is 0.008%, and the number of intermediate taps is 8 001.

Since x, y, and z are all integers, we have:

formula

That is, x is the integer of z/127, and y is the remainder of z/127.

1.2 Control Algorithm

Equations (5) and (6) are the basic formulas for realizing high-resolution digital potentiometers. For software design, the relationship between the middle tap position z of POT and the middle tap positions of POT0, POT1, POT2, and POT3 must also be established.

According to Figure 1, we can see that:

formula

Series potentiometer sliding end prohibition control

formula

2 Hardware Circuit

2.1 X9241 digital potentiometer

X9241 is a digital potentiometer produced by Xicor. It includes an I2C interface and four 64-bit digital potentiometers POTO, POT1, POT2, and POT3. Each digital potentiometer consists of a resistor array and a corresponding sliding end count register WCR, 4-bit data registers R0 to R3, etc. Its pin configuration is shown in Figure 3.

[page]

X9241 Pin Configuration

Each potentiometer consists of 63 resistor segments, and the physical terminals of each resistor array are equivalent to the fixed terminals (VH, VL) of the mechanical potentiometer. The VH and VL of each array and the contact points (i.e., taps) between each resistor segment are connected to the sliding output terminal through a FET switch, and the position of the sliding terminal in the resistor array is controlled by the slave WCR. Among them, VW, VW1, VW2, and VW3 are the sliding terminals of the four potentiometers, VL0, VL1, VL2, and VL3 are the low ends of the four potentiometers, and VH0, VH1, VH2, and VH3 are the high ends of the four potentiometers. If 2, 3, or 4 of the four resistor arrays are connected in series, a digital potentiometer with 127, 190, or 253 taps can be formed. The chip uses an I2C bus interface, and SDA and SCL are serial data and serial clock, respectively. A0 to A3 are chip address setting bits.

X9241 provides a method to connect arrays in series, which can connect 63 resistor elements in one array in series with resistor elements in an adjacent array. Its control bits are in the 3-byte instruction, and its data byte includes 6 bits (LSB) used to define the position of the sliding end plus the upper 2 bits: CM (series mode) and DW (disable sliding end). The data byte is as follows:

Data Bytes

2.2 Circuit Design

According to the design principle of FIG. 1 and the pin configuration diagram of FIG. 3 , the circuit design of a high-resolution digital potentiometer can be realized, as shown in FIG. 4 .

Circuit Design of High Resolution Digital Potentiometer

①SDA and SCL are the serial data and serial clock of the I2C bus, which are connected to the I/O line of the microcontroller. The microcontroller is the master device, and X9241 is the slave device. The device address is:

0 1 0 1 A3 A2 A1 A0

The upper 4 bits are fixed, and the lower 4 bits are determined by the wiring method of A3~A0. According to the wiring method of the circuit in Figure 4, the slave address of X9241 is 50H.

② In order to improve the linearity, a follower consisting of a first-stage operational amplifier can be added between VW0 and VL1, and a first-stage operational amplifier can also be added between VW3 and VH2. The improved circuit is shown in Figure 5.

Improved circuit

3 Programming

3.1 Read and write single digital potentiometer function design

According to the instruction structure and control timing of X9241, a program for reading and writing a single digital potentiometer can be written.

(1) Change the timing of the potentiometer middle tap command (write WCR) Take the write potentiometer POT0 as an example, set the middle tap WCR of potentiometer 0 to 20H (the maximum number of taps for each potentiometer of X9241 is 64, that is, the effective value is less than 63). The command control word is 101000000B, that is, AOH; if AOA1A2A3 are all connected to a low level in the circuit, the device address is 01010000B, that is, 50H. The command sequence is as follows:

Start→Send address 50H→Ack→Send command word A0H→ACK→Send 20H→ACK→Stop.

(2) Read the middle tap position command of the potentiometer (read WCR) Timing Take the reading of potentiometer POT1 as an example, and read back the middle tap WCR position value of potentiometer 1. The command control word is 100100000B, that is, 90H; if AOA1A2A3 are all connected to low level in the circuit, the device address is 01010000B, that is, 50H. The command sequence is as follows:

Start→Send address 50H→Ack→Send command word 90H→ACK→Receive 1 byte→ACK→Stop.

3.2 Main function design

The function of this function is to convert the middle tap position z of the designed digital potentiometer POT into the values ​​x0~x3 of the middle tap position registers WCR of four independent digital potentiometers POT0~POT3, and control the control bits CM and DW of POT1 and POT2 at the same time, as shown in Figure 6.

Program flow chart for controlling 4 independent digital potentiometers

In the flow chart, when y<64, the middle tap position of POT12 (POT1 and POT2 connected in series) is within the range of POT2, so the middle tap of POT1 is invalid, that is, DM1=1 is set; when y≥64, the middle tap position of POT12 is within the range of POT1, so the middle tap of POT2 is invalid, that is, DM2=1 is set.

Conclusion

The design of high-resolution digital potentiometers can be realized at a lower cost by using the software and hardware collaborative method. The good matching of the four digital potentiometers in the same chip and the application of voltage followers make the designed digital potentiometers have better linearity. In practical applications, in order to improve the load capacity, an output buffer needs to be connected to the sliding output terminal.

Reference address:Software Implementation of High Resolution Digital Potentiometer X9241

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