Design scheme based on four-channel synchronous underwater acoustic signal recorder

This scheme designed and developed an underwater acoustic signal recorder, which realizes the synchronous acquisition and storage of 4-channel 24-bit underwater acoustic signals, with a dynamic range of up to 100dB and a sampling rate of up to 100kS/s. The test results show that the recorder designed in this scheme has high accuracy, large dynamic range, low power consumption, large storage capacity, stable and reliable operation, and can complete the acquisition and recording of underwater acoustic signals below 30kHz.

　　1. Introduction

　　Hydroacoustic signals are the main information carrier for underwater detection, positioning, navigation, and communication. Analyzing, processing, and studying the original signals of underwater target echoes and their radiation noise can obtain a large amount of target characteristic information. This requires a multi-channel synchronous high-precision hydroacoustic signal acquisition and recording device to collect and record the original signals of underwater targets.

　　Traditional underwater acoustic acquisition systems often use single-channel A/D converters below 16 bits and single-chip microcomputers as core components, with low sampling accuracy, slow acquisition and storage speed, weak processing capabilities, and low versatility. Therefore, this paper uses 24-bit high-precision A/D converter ADS1274, ultra-low power digital signal processing chip TMSVC5509A and CF card as the main storage medium to design and develop a four-channel synchronous underwater acoustic signal recorder. The recorder has high accuracy, large dynamic range, low power consumption, large storage capacity, stable and reliable operation, strong versatility, and can complete the acquisition, recording and analysis of underwater acoustic signals below 30kHz.

　　2. Overall design of recorder

　　The underwater acoustic data recorder needs to work underwater for a long time, and its functions need to meet the requirements of large-capacity storage, low power consumption, high fidelity, and real-time acquisition and recording. Given that the frequency of underwater acoustic signals is generally not high, a sampling rate of 100kHz is sufficient to meet most signal acquisition requirements. The total amount of data collected by four channels of 24-bit for 8 hours does not exceed 32G, so a Compact Flash (CF card) with a capacity of 32G can meet the system storage requirements. When the sampling frequency of the recorder is 100kHz, the acquisition and storage of four channels of 24-bit underwater acoustic signals must be completed within a sampling period of 10μs, and the real-time requirements are relatively high. Here, TI's ultra-low power digital signal processing chip TMS320VC5509A is selected as the main control processor, and its processing speed reaches 400MIPS, which can meet the system requirements. According to the needs of the system, the system hardware part consists of four-channel signal conditioning (preamplification and filtering), high-precision analog-to-digital converter (AD), main control processor (DSP), data storage unit (CF card), and PC interface unit (USB), and the software part consists of data acquisition module, data storage module, and data reading module. The overall structure of the recorder is shown in Figure 1.

　　3. Recorder Hardware Design and Implementation

　　1. Signal conditioning part

　　The main function of the signal conditioning part is to amplify, filter, convert single-ended to double-ended, and boost the voltage of the weak signal received by the hydrophone so that the received hydrophone signal can meet the requirements of the A/D input signal after conditioning.

　　The signal of the hydrophone is weak, and the preamplifier plays a vital role in suppressing noise. Whether it can effectively suppress various noises is the key to the success of this system. Here, a mature commercial preamplifier module is used.

　　The technical indicators of the preamplifier module are: input mode: differential and single-ended; common mode rejection ratio: >100dB; input impedance: 200MΩ; noise voltage density is 3nV/; gain: 10 times (20dB).

　　(ii) A/D interface circuit

　　After repeated demonstration and comparison, and taking into account factors such as system performance, circuit structure, system power consumption, scalability and chip source, this system selected a 24-bit high-precision AD converter ADS1274 from TI of the United States. The AD chip integrates multiple independent high-order chopper-stabilized modulators and FIR digital filters, can realize 4-channel synchronous sampling, supports 4 working modes of high speed, high precision, low power consumption and low speed, has a bandwidth of 62 kHz, and the sampling frequency can reach up to 128KS/s. The chip adopts differential input, so the input end can be directly connected to the sensor or a small voltage signal; the working mode can be selected by setting the corresponding input/output pins, without register programming, and its data output can select frame synchronization or SPI serial interface, which is convenient for connecting to DSP and can meet the strict requirements of multi-channel weak signal acquisition applications.

　　(III) Main controller

　　The main controller is the core of the system. The main control processor selected for this system is TI's TMS320VC5509A, which is one of the TMS320C5000 series DSP chips produced by TI. The C5000 series DSP is widely used in mobile communication terminals, among which C54x is the most mature. It adopts an improved Harvard structure and integrates rich hardware logic and external interface resources, which not only improves performance but also reduces cost and volume. C55x is developed on the basis of C54x. It has all the advantages of C54x and is the new product with the lowest power consumption. The low power consumption of C55x meets the power consumption requirements of underwater energy-constrained electronic systems.

　　(IV) CF card controller

　　CF supports three basic working modes: PC Card Memory mode, PC Card I/O mode and True IDE mode. This article uses the True IDE mode, which can be automatically entered when the CF card is powered on. Before inserting the CF card, ensure that the /OE pin of the CF card slot is low, which can make the CF card enter the True IDE mode. The interface diagram of DSP and CF card is shown in Figure 4.

　　A3-A0 are the data, command or status register address lines. D15-D0 are the data bus. CD1 and CD2 are the hardware detection pins for the existence of the CF card, which are connected to the ground internally. When the CF card is effectively inserted into the card holder, the corresponding CD1 and CD2 on the card holder are pulled low, and the existence of the CF card can be determined by hardware or software. RDY/BSY is the CF card status signal. When the CF card is busy, this pin is set low. At this time, the DSP cannot access it or perform other operations. WE and OE are valid read and write signals. REG is the register selection signal line. When -REG is high, the data memory (command or data) is accessed, and when it is low, the attribute memory is accessed. When powered on, the CF card automatically completes the reset and enters the memory mode in the default state. The CF card can also be reset by an external controller through the RESET pin. Figure 5 is a physical picture of the hardware circuit board of the recorder.

　　4. System software design

　　The focus of system software design is to complete the storage of collected data, that is, to complete the reading and writing operations on the CF card.

　　When the DSP reads and writes the CF card sector, first set the LBA address of the starting sector and the number of sectors; then set the command register, read the data setting command "20H", and write the data setting command "3 0 H"; then read the status register to determine whether the status register value is "5 8 H". If so, start the read and write operation. If not, continue to read the status register. Next, read whether the status register is "50H" to determine whether the CF card operation is completed. If not, continue to read and judge; if yes, end the read and write process. If a timeout or error occurs in the judgment status register, the timeout or error flag can be set to jump out of the read and write process. Figure 6 is a flow chart of reading and writing a sector of a CF card.

　　V. Conclusion

　　This paper mainly proposes a design scheme based on a four-channel synchronous underwater acoustic signal recorder, aiming at the low precision and energy-limited characteristics of traditional underwater information collection equipment. The scheme uses ADS1274, MSVC5509A and CF card as core components to realize the synchronous collection and recording of 4-channel signals. The designed circuit board is about 16cm×12cm and powered by a high-energy lithium battery. The whole system can be easily installed in a cylindrical sealed tank with an inner diameter of 15cm and a height of 20cm.

　　A noise test experiment proved that the recorder designed in this scheme has a small size, low power consumption (about 2W) and large storage capacity. It can stably and reliably collect and store underwater environmental noise and target radiation noise data in real time, and has good engineering application prospects.