Design of PLC backplane bus protocol interface chip based on single chip microcomputer and CPLD (Part 1)

Abstract: A set of PLC backplane bus protocol interface chips based on CPLD is designed. The protocol chip can distinguish the periodic data and non-periodic data of the PLC backplane bus. The process of designing the state machine, protocol frame controller, and FIFO controller using Verilog HDL language is introduced in detail. The experimental results of stable operation of the backplane bus at 25MHz verify the feasibility of the protocol chip design.

　　The programmable logic controller (PLC) host supports the connection of expansion modules through the backplane bus. The backplane bus is a high-speed data path between the PLC host and the I/O expansion module, supporting the I/O data refresh between the host and the expansion module. The technical level of the backplane bus determines the I/O expansion capability of the PLC product and is the core technology of PLC design and manufacturing. At present, most PLCs use serial communication technology to implement the backplane bus. The serial bus has fewer leads and lower hardware cost. Compared with the parallel bus, it is not easily interfered. The serial bus can improve the reliability of automation equipment in harsh factory and industrial environments. The optional types of serial communication technology include I2C, UART, SPI, USB and Ethernet. Generally speaking, many single-chip microcomputers as PLC main chips have integrated these peripheral components. However, the communication rate of the I2C, UART, and SPI peripherals integrated in the single-chip microcomputer is too slow to meet the communication speed requirements of the backplane bus. Although the communication speed of USB and Ethernet is very fast, since they are universal interfaces, the microcontroller needs to intervene in the communication protocol processing. The microcontroller processes data slowly, so the overall communication speed is still very slow. A large PLC generally takes less than 1ms to collect thousands of I/O data points. To meet such high-speed communication requirements, a special backplane bus must be designed.

　　1 Backplane bus working principle

　　As shown in Figure 1, the data communication process based on the backplane bus is as follows:

　　(1) The PLC host's command is sent to the backplane bus through the host protocol chip; (2) The slave protocol chip sends the received command to the expansion module's microcontroller. The microcontroller of one of the expansion modules responds and sends the response data to the backplane bus through the slave protocol chip; (3) The host protocol chip receives the response data and sends it to the microcontroller of the PLC host.

Figure 1 Backplane bus communication block diagram

　　The data sent by the PLC host to the backplane bus can be divided into two categories: one is I/O refresh data, which is periodic and data exchange is very frequent; the other is diagnostic data, which is non-periodic and has a low chance of occurrence.
2 Protocol Chip Design

　　This design defines that the backplane bus adopts specifications similar to SPI serial communication. There are 4 leads for communication, including clock signal SCLK, chip select signal SSEL, write data lead MISO and read data lead MOSI; it supports the host and slave to send and receive data at the same time. The data bit format is shown in Figure 2. The data frame is transmitted when the SSEL signal is low.

Figure 2 Backplane bus data specifications

　　The signals include data/address signal, reset signal Reset, and interrupt signal INT.

　　The internal structure block diagrams of the host and slave protocol chips are the same, as shown in Figure 3.

　　The protocol chip has a state machine controller, frame controller, shift register, receive/transmit FIFO and read/write cache inside. The periodic and non-periodic data frames sent by the microcontroller are first written to the write cache, queued and sent in the transmit FIFO, and the data frames are converted into serial data and sent to the backplane bus under the drive of the SPI clock SCLK; under the action of the SPI clock, the serial data from the backplane bus is received; under the coordination of the state machine and the frame controller, the valid data frames in the receive FIFO are extracted and put into the read cache area, waiting for the microcontroller to read. If it is non-periodic data, an interrupt signal is sent to notify the microcontroller to fetch the data. The periodic data in the read cache can be overwritten, and the newly received periodic data directly overwrites the old periodic data, while the non-periodic data is stored separately and cannot be overwritten. It is read and cleared by the microcontroller.

Figure 3: Internal structure diagram of the protocol chip

　　The protocol chip allows the external MCU to access the read cache and write cache when idle, so the MCU does not have to frequently process periodic data through interrupt technology, and the PLC host can access the periodic data of the slave without waiting.

　　3 CPLD-based protocol chip implementation

　　3.1 CPLD chip selection

　　This design uses the MachXO series chips from Lattice. This series of CPLDs integrates some FPGA functions. In addition to the built-in rich LUT resources, it also has a large number of distributed SRAM bits and embedded SRAM blocks dedicated to FIFO design. It also has an analog phase-locked loop (PLL) to support clock signal multiplication and division, etc. The I/O pins can be configured to be compatible with 1.2/1.5/1.8/3.3V levels.