Design of PLC backplane bus protocol interface chip based on single chip microcomputer and CPLD (Part 2)

3.2 Hardware Programming Based on Verilog HDL Language

　　This design uses Verilog HDL language to program the protocol chip. Verilog HDL language is a hardware description language. When designing digital chips, it can be described in layers and can perform timing modeling. This design uses a mixed design mode. The main design modules include state machine, protocol frame detection, FIFO controller design, etc.

　　1) State machine design.

　　The top module of the protocol chip is the state controller part. The protocol chip has four states, which are respectively processed by the state machine description pseudo code based on the Verilog HDL programming language as follows:

　　2) Protocol frame detection.

　　The frame checksum of this protocol chip is performed in a simple addition form. On the receiving side, if the sum of the useful data in the data frame is the same as the subsequent checksum byte, the protocol is correct, otherwise the frame is discarded. The code for calculating the protocol frame checksum is as follows:

　　3)FIFO design.

　　FIFO utilizes the resources of the embedded SRAM block of the MachXO series CPLD. Lattice's ispLEVER 7.0 software provides a configurable IP soft core, which can be implemented based on the embedded SRAM block or using a lookup table. The block diagram of the FIFO IP core is shown in Figure 4. The configurable parameters of the FIFO include FIFO byte depth, EmptyFull, Almostempty and AlmostFull trigger byte depth, data width, big-endian and little-endian modes, etc.

　　Figure 4 Configurable FIFO Controller IP Soft Core Block Diagram

3.3 Protocol Chip Synthesis

　　The Verilog HDL program was compiled and synthesized by Lattice's CPLD development software ispLEVER 7.0. After many attempts, the MachXO2280 chip in Lattice's MachXO series CPLD was finally selected. The synthesized host protocol chip occupies about 60% of the CPLD resources, and the slave protocol chip occupies about 45% of the CPLD resources. The FIFO controller makes full use of the embedded RAM block inside the MachXO2280 chip, and uses the phase-locked loop to achieve high-frequency clock operation. Finally, the LSC ispVM(R)System burning software was downloaded to the CPLD chip through the JTAG port to perform protocol chip function verification tests.

　　4 Conclusion

　　The backplane bus protocol chip designed in this paper works stably and passes the group pulse test when the backplane serial bus clock frequency is 25MHz, the signal level is LVTTL, the bottom plate lead length is 40cm, and 1 host is connected to 3 expansion modules, which verifies that the design of this set of protocol chips is successful. Since this set of protocol chips is specially designed for the periodic and non-periodic data transmission of PLC, the hardware-implemented protocol frame controller supports high-speed communication and data frame verification functions, avoiding data transmission errors, greatly reducing the software overhead of the peripheral microcontroller, and enhancing reliability. It is a set of protocol chips that are very suitable for PLC backplane buses or backplane bus system protocol chips that require multi-module collaboration.