Design of Digital Down-Conversion in Shortwave Channel Simulator

introduction

Shortwave communication channels have the characteristics of time-varying and dispersion, and are easily interfered by noise, so simulating their transmission characteristics has high practical value. Shortwave channel simulators use advanced simulation technology to realize communication tests in laboratory environments. Because of their effectiveness, economy, safety and intuitiveness, they can be widely used in communication tests. Most traditional shortwave channel simulators stay on the voice bandwidth, and their main shortcomings are high power consumption, large size, low controllability and poor real-time performance. The rapid development of analog-to-digital converter (A/D) devices and digital signal processing theory has laid a solid foundation for the development of broadband shortwave channel simulators. However, due to the limited processing speed of existing digital signal processors (DSPs), it is often difficult to directly process the digital signals obtained by high-speed A/D sampling in real time. In order to solve this contradiction, digital down-conversion (DDC) technology is needed. Therefore, digital down-conversion technology plays an important role in the digitization and softwareization of broadband shortwave channel simulators. FPGA has high processing speed and strong stability, and is flexible in design, easy to modify and maintain. At the same time, it can use different structures to complete corresponding functions according to different system requirements, greatly improving the applicability and scalability of the system. Therefore, FPGA has gradually become the first choice for implementing DDC.

1 Design of broadband shortwave channel simulator

The input of the broadband shortwave channel simulator is the shortwave modulation signal (3~30 MHz). First, it is directly sampled by high-speed A/D to convert the analog modulation signal into a digital signal, and then the I and Q digital baseband signals are separated by digital down-conversion technology to facilitate subsequent digital signal processing. During signal processing, the channel parameters are set and output through the display control device. Finally, after the processed signal is converted by D/A, it is output through low-pass filters, amplifiers, and program-controlled attenuation devices to output the final required analog signal. This greatly reduces the performance requirements of ADC and DSP devices, reduces the burden of digital signal processing, facilitates implementation and effectively reduces costs. The architecture of the broadband shortwave channel simulator is shown in Figure 1.

Figure 1 Architecture of broadband shortwave channel simulator

The broadband shortwave channel simulator reduces the sampling data rate through digital down-conversion, reducing the pressure of subsequent signal processing. Digital down-conversion plays a bridge role between the front-end ADC and the back-end DSP devices in the simulator. In the digital down-conversion part, the received signal frequency band and filter characteristics can be easily programmed and controlled, which greatly improves the performance and flexibility of the broadband shortwave channel simulator, and is very convenient for system upgrades or compatibility.

2 FPGA-based digital down-conversion implementation solution

The input frequency of broadband shortwave modulation signal is 3~30 MHz. According to bandpass sampling theory, in engineering implementation, the signal sampling rate is generally about 2.5 times the analog signal bandwidth. Considering that the sampling frequency can be increased as much as possible under the premise that the device meets the requirements, 64 MHz is selected as the sampling frequency of ADC. After 32 times frequency conversion of digital down-conversion, the signal bandwidth finally output to DSP is 2 MHz.

The DDC implementation in this paper does not use the IP core provided by Altera, which can reduce costs and reduce dependence on foreign technology.

The FPGA device uses cyclone III device, which is a new generation of low-cost FPGA using SRAM process from Altera. The characteristics of this series of devices are low cost, low power consumption and high performance. It has an embedded multiplier to realize special multiplication and multiplication-addition operations, and can also realize finite impulse response (FIR) filter; there are up to 20 global clocks, supporting dynamic clock management to reduce power consumption in user mode; and there are 4 phase-locked loops (PLL). According to the data processing requirements of the design, the resources required for processing are estimated, and the principle that the pin package is conducive to board making, the EP3C40Q240C8N FPGA is selected, and the design, synthesis and simulation of the signal generator are carried out on the development tool Quartus II.

2.1 Design of digital controlled oscillator

NCO is one of the main factors that determine the performance of DDC. The goal of NCO is to generate orthogonal sine and cosine sample signals with variable frequency.

NCO is implemented by direct digital synthesis (DDS). Currently, common technologies include table lookup and CORDIC calculation. In the case of ultra-high-speed signal sampling frequency of software radio, real-time calculation of NCO is difficult to achieve. At this time, the most effective and simple method for sine samples generated by NCO is table lookup, that is, the sine value of the phase is calculated in advance according to the phase of each NCO sine wave, and the sine value data of the phase is stored according to the phase angle as the address. The principle diagram is shown in Figure 2.

Figure 2 Schematic diagram of NCO based on table lookup method

In Figure 2, the 32-bit accumulator consists of a 32-bit adder and a 32-bit register. Under the action of the clock, the adder sends the output data to an input end of the adder through the register, and performs an addition operation with the 32-bit frequency control word to obtain a regular phase accumulation result. The lookup table is actually a read-only memory ROM that stores the amplitude encoding of the sampling points of the sine signal, but the size of the ROM table increases exponentially with the increase of the address bits. Therefore, in order to meet the signal performance without reducing the address bits of the lookup table, an optimization method must be used to reduce the size of the ROM table. According to the symmetric characteristics of the sine wave, only the amplitude of a quarter cycle needs to be stored, and then the amplitude of the entire cycle can be restored through the corresponding conversion. At the same time, since the phase difference between the cosine wave and the sine wave is ??/2, the cosine signal can be easily realized.

After completing the design of the NCO module of the DDC, the input signal that needs to be down-converted is multiplied with the two orthogonal local oscillator signals generated by the NCO to complete the digital mixing orthogonal transformation, that is, to complete the spectrum shifting.

2.2 CIC filter design

The CIC integrator comb filter is a very effective unit for high-speed decimation. The unit impulse response of the CIC filter is:

From formula (2), it can be seen that the CIC filter consists of two parts, namely, the integrator and the comb filter cascade. Its implementation is very simple, with only addition and subtraction operations, no multiplication operations, and a very high processing rate can be achieved when implemented in FPGA. However, the sidelobe level of a single-stage CIC filter is only 13.46 dB lower than the main lobe, which means that the stopband attenuation is very poor and generally difficult to meet practical requirements. In order to reduce the sidelobe level, a multi-stage CIC filter cascade can be used to solve the problem.

The band content difference of N-stage CIC filter cascade is N times that of single-stage CIC filter, which means that multi-stage CIC filter cascade increases stopband attenuation while also increasing the band content difference. Therefore, the number of CIC filter cascades is limited and should not exceed 5 stages.

In this design, the CIC filter needs to complete 16-fold decimation, which is achieved by 5-stage cascade. The bit width of the input and output parts is 12 bits. The results of MATLAB simulation are shown in Figure 3.

Figure 3 CIC filter amplitude characteristics

After passing through the CIC filter, the signal sampling rate is decimated by 16 times to 4 MHz, thus realizing the decimation function while also reducing the sampling rate.

2.3 Half-band filter

The so-called half-band filter is a FIR filter whose frequency response satisfies the following relationship:

The HB filter is used as the second-stage low-pass filter and decimation because almost half of its coefficients are 0 and the amount of computation required for filtering is reduced by half.

The HB decimation factor is fixed at 2, which is particularly suitable for the requirement of reducing the sampling rate by half. After decimation by CIC and HB filtering, the baseband signal is reduced from the initial high data rate to a lower rate, which is suitable for post-stage FIR processing.

2.4 FIR low-pass filter design

The last module of the digital down converter is a low-pass FIR filter, which is mainly used to perform signal shaping and filtering without extraction.

After the signal passes through the CIC and HB filters, the sampling rate of the signal input to the FIR filter is relatively low. Therefore, at a certain processing clock rate, a higher-order FIR filter can be used, so that the filter's passband fluctuation, transition band bandwidth, stopband minimum attenuation and other indicators can be well designed.

Call MATLAB's Filter design to obtain the filter coefficients. Design a FIR with a passband cutoff frequency of 2 MHz in MATLAB, and import the filter coefficients into the FIR of FPGA; the higher the order (coefficient length) of the FIR, the better the performance, but considering the resource usage, the order of the FIR should not be too high. This design uses a 37-order FIR.

3 Simulation results of DDC system based on FPGA

According to the above design analysis results, the FPGA program was written and simulated on the Quartus II platform. The short-wave modulation signal with a sampling rate of 64 MHz was input and synthesized and simulated for the EP3C40Q240C8 device of the Cyclone III series, as shown in Table 1.

Table 1 Timing simulation diagram of DDC implementation

After the input signal passes through the mixer, it is then decimated by 16 times by the CIC filter, decimated by 2 times by the half-band filter, and shaped and filtered by the FIR filter, and finally outputs two orthogonal signals, I and Q. As shown in Table 1, Data In is the input signal, DDC Data I is the output in-phase component, and DDC Data Q is the output orthogonal component. After the 64MHz sampling signal is mixed by the NCO, decimated by 16 times by the CIC filter and 2 times by the HB filter, it becomes a 2 MHz signal and is shaped and output by the FIR filter. From Table 1, it can be seen that the designed DDC has the function of speed reduction and down-conversion for high-speed sampled signals, and the processing bandwidth is greatly reduced, so the requirements for the processing speed of subsequent devices are reduced.

There are still some glitches in the simulation, which are caused by inaccurate delay control of the signal. The size of the delay is not only related to the length of the connection and the number of logic units, but also to the manufacturing process and working environment of the device. The elimination of glitches is a problem to be solved.

4 Conclusion

Based on the analysis of the working mechanism of broadband shortwave channel simulator and the principle of digital down-conversion, the digital down-conversion based on FPGA is designed in combination with Matlab algorithm simulation technology. Functional and timing simulation results show that the digital down-conversion function implemented based on FPGA design meets the performance requirements of broadband shortwave channel simulator. This design method reduces the dependence on FPGA IP core, improves the processing rate of DDC, realizes programmable digital carrier control and extraction filter, has great flexibility and versatility, is of great significance for the realization of broadband shortwave channel simulator, and can be promoted to other occasions where down-conversion is required.