DAC and its buffer help improve system performance and simplify design

This article examines a new precision 16-bit DAC and discusses some ideas for output buffering of high-speed complementary current-output DACs with transformer-like performance.

Voltage-switched 16-bit DAC offers low noise, fast settling time and improved linearity

Resistor-ladder multiplying DACs based on the breakthrough 10-bit CMOS AD7520—introduced nearly 40 years ago—were originally used with an inverting op amp, with the amplifier’s summing junction (IOUTA) providing a convenient virtual ground (Figure 1).

Figure 1. CMOS multiplying DAC architecture.

However, under certain restrictions, they can also be used in a voltage-switching configuration to provide a noninverting voltage output, where the op amp acts as a voltage buffer (Figure 2). Here, the reference voltage, VIN, is applied to OUT, and the output voltage, VOUT, is provided by VREF. Soon after, 12-bit versions optimized for this use became available.

Figure 2. Multiplying DAC in voltage switching mode.

Fast forward to today: As single-supply systems become more prevalent, designers face the challenge of controlling power consumption while maintaining performance levels at higher voltages. There is also an increasing demand for higher resolution devices (up to 16 bits) that can be used in this mode.

The significant advantage of using a multiplying DAC in voltage switching mode is that no signal inversion occurs, so a positive reference voltage results in a positive output voltage. However, the R-2R ladder architecture also has a drawback when used in this mode. The nonlinear resistance of the N-channel switch in series with the R-2R ladder resistors will cause the integral linearity (INL) to degrade relative to the same DAC used in current steering mode.

To overcome the shortcomings of multiplying DACs while maintaining the advantages of voltage switches, new high-resolution DACs have been developed, such as the AD5541A, as shown in Figure 3. The AD5541A uses a partially segmented R-2R ladder network and complementary switches to achieve ±1-LSB accuracy at 16-bit resolution, no adjustment required over the entire rated temperature range of -40°C to +125°C, and a noise value of 11.8 nV/√Hz with a settling time of 1?s.

Figure 3. AD5541A architecture.

Performance characteristics

Settling Time: Figure 4 and Figure 5 compare the settling time of a multiplying DAC in voltage mode and the settling time of the AD5541A. When the capacitive load on the output is minimal, the settling time of the AD5541A is approximately 1 µs.

Figure 4. Settling time of a multiplying DAC.

Figure 5. Settling time of the AD5541A.

Noise Spectral Density: Table 1 compares the noise spectral density of the AD5541A and the multiplying DAC. The AD5541A has a slight advantage at 10 kHz and a significant advantage at 1 kHz.

Table 1. Noise Spectral Density of the AD5541A and Multiplying DAC

Integral nonlinearity: Integral nonlinearity (INL) measures the maximum deviation between the ideal output of a DAC and the actual output after gain and offset errors are excluded. Switches in series with the R-2R network can affect the INL. Multiplying DACs typically use NMOS switches. When used in voltage switching mode, the source of the NMOS switch is connected to the reference voltage, the drain is connected to the ladder resistor, and the gate is driven by the internal logic (Figure 6).

Figure 6. Multiplying DAC switch.

For current to flow in an NMOS device, VGS must be greater than the threshold voltage, VT. In voltage switching mode, VGS = VLOGIC – VIN must be greater than VT = 0.7 V.

The R-2R resistor ladder of a multiplying DAC is designed to distribute the current equally to each pin. This requires that the total resistance to ground (seen from the top of each pin) be exactly the same. This is achieved by adjusting the switches, where the size of each switch is proportional to its on-resistance. If the resistance of one pin changes, the current flowing through that pin will change, resulting in linearity errors. VIN cannot be so large that the switch turns off, but it must be large enough to keep the switch resistance low because changes in VIN affect VGS, resulting in a nonlinear change in on-resistance, as shown below:

This change in on-resistance will unbalance the current and degrade linearity. Therefore, the supply voltage on the multiplying DAC cannot be reduced too much. Instead, the reference voltage must not exceed AGND by more than 1V to maintain linearity. For a 5V supply, linearity will begin to degrade when changing from a 1.25V reference voltage to a 2.5V reference voltage, as shown in Figures 7 and 8. When the supply voltage is reduced to 3V, linearity will completely break down, as shown in Figure 9.

Figure 7. INL of IOUT Multiplying DAC in Inverting Mode, ( VDD = 5 V, VREF = 1.25 V)

Figure 8. INL of IOUT Multiplying DAC in Inverting Mode (VDD = 5 V, VREF = 2.5 V)

Figure 9. INL of a multiplying DAC in inverting mode (VDD = 3 V, VREF = 2.5 V)

To reduce this effect, the AD5541A uses complementary NMOS/PMOS switches, as shown in Figure 10. The total on-resistance of the switch now comes from the combined contribution of the NMOS and PMOS switches. As shown previously, the gate voltage of the NMOS switch is controlled by internal logic. An internally generated voltage, VGN, sets the ideal gate voltage so that the on-resistance of the NMOS is balanced with that of the PMOS. The size of the switch is adjusted by code so that the on-resistance adjusts with code. Therefore, the current will adjust up or down and accuracy will be maintained. Since the impedance of the reference input changes with code, it should be driven by a low impedance source.

Figure 10. Complementary NMOS/PMOS switch.

Figure 11 and Figure 12 show the INL performance of the AD5541A for 5 V and 2.5 V reference voltages.

Figure 11. INL of AD5541A ( VDD = 5.5 V, VREF = 5 V)

Figure 12. INL of AD5541A ( VDD = 5.5 V, VREF = 2.5 V)