High-voltage DAC powered from low-voltage supply generates tuning signal for filter

Circuit Function and Advantages

The circuit shown in Figure 1 generates a high voltage signal that controls the capacitance of a BST (barium strontium titanate) capacitor. The BST capacitance can be changed by simply applying 0 V and 30 V to the correct terminals. In this way, the dielectric thickness changes and, therefore, the capacitance. BSTs are often used to tune antenna arrays and tunable filters. They offer clear advantages in particular for these tuning applications, such as compensating for component tolerance errors, precisely tuning filter cutoff frequencies, or impedance matching networks for tunable antennas.

Such applications require a convenient, compact, and low-cost circuit to generate a high voltage supply, and adding a separate power supply just for this function is usually not practical. The circuit in Figure 1 meets this requirement using the ADP1613 boost converter and the AD5504 30 V/60 V DAC. The total board area for the boost regulator circuit is only 43 mm2. The ADP1613 is available in an 8-lead MSOP package, and the AD5504 is available in a 16-lead TSSOP package.

The boost circuit can also be used in LED driver applications and to provide receiver bias voltage in optical communication systems.

Figure 1. A boost supply and high-voltage DAC provide the tuning signal for the BST capacitor (simplified schematic: all connections not shown)

Circuit Description

The circuit can be powered by 3 V (VDD), and the BST capacitor needs a voltage of more than 20 V to achieve full control. The two main circuit blocks are the ADP1613 boost switching converter and the AD5504 high voltage DAC. The circuit diagram is shown in Figure 1.

The ADP1613 is a step-up DC-DC switching converter with an integrated power switch capable of providing an output up to 20 V. Higher output voltages can be achieved using additional external components. The ADP1613 features an adjustable soft start function to prevent inrush current when the device is enabled. The pin-selectable switching frequency and PWM current mode architecture provide easy noise filtering and excellent transient response. The components connected around the ADP1613 can generate a 32 V output from a 3 V input.

The ADIsimPower™ design tool provides designers with an easy way to decide the appropriate components based on the input and output requirements. The ADP1613 circuit design shown in Figure 1 uses the “lowest cost” option of ADIsimPower with a 3 V input voltage, 32 V output voltage, and 40 mA load current.

The ADIsimPower design files include a bill of materials, detailed schematics, Bode plots, efficiency graphs, transient response, and a recommended board layout.

The 32 V output of the ADP1613 is used as the power supply for the AD5504. The AD5504 is a quad, 12-bit DAC capable of providing output voltages up to 60 V. The full-scale output of the AD5504 is determined by the state of the R_SEL pin. In this application, R_SEL is connected to VDD, so a full-scale output of 30 V is selected. The AD5504 is controlled by a 3 V logic-compatible serial interface. The DAC output is changed by writing to the appropriate DAC register through the serial interface. Multiple DACs can be updated simultaneously by pulsing the load DAC ((LDAC)) pin low, thereby changing all four BST capacitors simultaneously.

Using the circuit shown in Figure 1, a DAC output voltage of up to 30 V can be generated. The output voltage is used to set the bias voltage of the BST capacitor, which in turn adjusts the antenna response. Figure 2 shows the equivalent circuit of the BST capacitor used as an adjustable matching network, and Figure 3 shows the transfer function of the BST capacitance versus bias voltage and the resulting antenna response.

Figure 2. BST capacitor equivalent circuit

[page]In any circuit where accuracy is important, careful consideration must be given to the layout of the power supply and ground return on the board. The printed circuit board (PCB) containing this circuit should separate the analog and digital sections. If the circuit is placed in a system where other devices require an AGND to DGND connection, make the connection at only one point. This ground point should be as close to the AD5504 as possible. A multilayer PCB with large area ground and power planes should be used for this circuit.

The power supply to the AD5504 should be bypassed with 10 μF and 0.1 μF capacitors. These capacitors should be placed as close to the device as possible, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitor should be a tantalum bead or ceramic type. The 0.1 μF capacitor must have low equivalent series resistance (ESR) and low equivalent series inductance (ESL), characteristics that are common to ceramic types. The 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching.

The power supply traces should be as wide as possible to provide a low impedance path and reduce the effects of glitches on the power supply line. Clocks and other fast switching digital signals should be shielded from other devices on the board by digital ground.

Figure 3: Bias voltage vs. BST capacitance and resulting antenna response

Common changes

Depending on system requirements, other boost regulators can be used instead.

Circuit Evaluation and Testing

The circuit of Figure 1 is tested by applying a 3 V supply to VDD. This provides a 32 V supply to the AD5504 (measurable at pin 14) and also provides the VLOGIC supply to the AD5504. A microcontroller, DSP, or FPGA is used to provide the appropriate digital interface signals to the AD5504.

For normal operation, CLR should be high. SYNC, SCLK, and SDATA should be operated as described in the AD5504 data sheet to write data to the various registers of the AD5504. When data is written to a DAC register with LDAC low, the corresponding output is updated immediately. When data is written to a DAC register with LDAC high, the DAC output will hold its current value until a pulse is sent to pull LDAC low.