Characteristics and applications of 14-bit serial A/D converter MAX194

    Abstract: MAX194 is a 14-bit successive approximation serial output analog-to-digital converter. It has the characteristics of high speed, high precision, low power consumption, etc., and brings a sample and hold circuit, with a 10μA shutdown mode, which can meet the highest requirements. Conversion with a sampling frequency of 85kPS. Its fastest conversion time is 9.4μs, it has two input modes of unipolar and bipolar and three-state serial data output. At the same time, the price is much lower than the parallel output analog-to-digital converter with the same function. The article introduces its functions and uses, and also provides the hardware circuit and software program for MAX194 to interface with a single sleeper in the boiler temperature measurement system.

In some real-time data acquisition and information processing circuits, in order to meet the accuracy and speed requirements of data acquisition, AD converters with high resolution and fast conversion speed must be used. MAX194 is a high-precision, high-speed fourteen-bit serial AD converter with sample and hold with superior performance. The author applied the MAX194 chip in the project practice and achieved good results. Since the output mode of MAX194 is serial output and is different from the general parallel output mode, there are some matters that need to be paid attention to when communicating with MC51 series microcontrollers. Here the author introduces the problems encountered in the application and the solutions.

1 Working principle and structure

The working principle block diagram of MAX194 is shown in Figure 1. It mainly consists of main DAC, control logic, comparator and calibration DAC. The main DAC is used to generate an analog signal that is compared with the input analog signal. Its internal structure is different from the DAC inside a general analog-to-digital converter. It does not use a T-shaped resistor network, but consists of a capacitor array with binary weights ( See Figure 2). The analog electronic switch is controlled by the digital code of the digital quantity. When the code is 0, the switch is grounded, and when the code is 1, the switch is connected to the reference voltage. In this way, when d13 is 1 and the others are 0, VA=VREF/2; when d12 is 1 and the others are 0, VA=VREF/2 2; and so on, until when d0=1 and the others are 0, VA= VREF/2 14. According to the superposition principle, the total equivalent potential is:

VA=d13VREF/2+d12VREF/2 2……+d0VREF/2 14

Taking unipolar input as an example, the specific conversion process is as follows:

(1) Connect the free ends of the capacitor to AIN so that the capacitor can be charged to obtain the voltage VAIN.

(2) Connect the highest-order capacitor to the reference voltage, and connect the free ends of other capacitors to ground, so that VA=VAIN, that is, d13=1 and other bits are 0. At this time, VA=VREF/2-VAIN. When VA<0, that is When VAIN

(3) The second highest bit must be determined through the comparator and control logic, and so on. After 16 comparisons, the conversion can be completed (including two additional bits). It should be noted that the DUMMY capacitor in the picture is set up to give the capacitor in front of it a weight, and it itself has no weight. The DAC composed of capacitors will enable the MAX194 to have a sample and hold function, which means that the circuit does not need to add a sample and hold part.

In addition, the MAX194 itself has a calibration function that can be calibrated when powered on. When the external environment changes (such as temperature changes, power supply voltage changes, etc.), you can also manually set RESET to 0 for calibration.

2 Pin arrangement and functions

The pin arrangement of MAX194 is shown in Figure 3. It is packaged in a 16-pin DIP, and the functions of each pin are as follows:

Pin 1 (BP/UP/SHDN) is a three-state input. If this pin is left unconnected, the analog signal is input in a bipolar mode; when connected to high level, it is input in unipolar mode; when connected to low level, it operates in 10μA shutdown mode. .

Stop working when pin 10 (RESET) is connected to low level, and start calibration on the rising edge.

After pin 9 (CONV) goes low, A/D conversion begins.

Pin 7 (EOC) is the conversion end output. When the conversion ends, it outputs a low level, and then changes to a high level when the next conversion begins.

Pin 2 (CLK) is connected to an external conversion clock, with a maximum frequency of 1.7MHz; if pin 3 (SCLK) reads the result after the conversion is completed, it will be read at the frequency of SCLK. It can be at a different frequency than CLK, up to 5MHz.

Pin 5 (DOUT) is the serial data output pin, and the highest bit is output first.

Pin 8 (CS) is the chip select signal, allowing serial output.

Pin 12 (REF) is the reference voltage input terminal, and the output range is 0~5V.

Pin 11 (AIN) is an analog input, and the input range is 0~VRFEF or -VREF~+VREF.

Pins 6 and 14 (DNCD, AGND) are digital ground and analog ground respectively.

Pins 4 and 16 (VDDD, VDDA) are +5V digital power supply and +5V analog power supply respectively.

Pins 11 and 15 (VSSD, VSSA) are -5V digital power supply and -5V analog power supply respectively.

3 Application circuit of MAX194

MAX194 can be widely used in industrial control, measurement, digital signal processing, etc.

Figure 4 shows the interface circuit that the author uses MAX194 to interface with a single-sleep machine in the boiler temperature measurement system. The interface connects CS to the P2.7 pin, and the chip select signal is sent out by the software. The time pulse CLK used for conversion is generated by the ALE pin of 89C51. The TXD of 89C51 is connected to SCLK via the NOT gate to be used as a clock for reading data.

There are two ways to read out the conversion result, one is to read out at the clock frequency of CLK during the conversion process, and the other is to read out at the clock frequency of SCLK after the conversion is completed. The author chooses to read the results after the conversion is completed (the second method). In this method, after the conversion is completed, when EOC becomes low and CS is also low, the highest bit is output on DOUT, and then the other bits are output in sequence on the falling edge of SCLK. The highest frequency allowed by SCLK is 5MHz. Figure 5 is its timing diagram.

In the figure, tCONV is the conversion time; tCSS is the time of CS falling mode edge; tCSH is the time from the last falling edge of SCLK to the rising edge of CS.

4 Notes

    When using the circuit in Figure 4 for interface design, you should pay attention to the following points;

(1) Tcss must be greater than 75μs. CS should be set to zero in the program before sending the conversion start signal.

(2) The conversion start pulse must be synchronized with the conversion clock. For this reason, an OR gate should be added between P1.0 and ALE and then connected to CONV to ensure synchronization.

(3) When TXD is directly connected to SCLK, since 89C51 reads on the falling edge of TXD, and the first falling edge of TXD (SCLK) starts to output the second highest bit, the highest bit will be lost. For this purpose, an inverter can be connected between TXD and SCLK, so that when data is read in on the falling edge of TXD, DOUT can output data on the rising edge of TXD (the falling edge of SCLK). Since the reading of data and the output of data are carried out in time sharing, this full data output method of reading the highest bit first and then outputting the second highest bit is ensured.

(4) Since in the receive buffer SBUF, the storage order of data is:

Therefore, the order must be rearranged in the program. Figure 6 is the program block diagram. The specific program is as follows:

ADZHUAN：CLR PSW

CLR C

CLR P2.7

MOV P0, #02H

MOV R1, #03H

SETB P1.0

CLR P1.0

SETB P1.0

SETB P3.2

HERE: JB P3.2, HERE

LOOP: MOV SCON, 10H

WAIT1: JNB RI, WAIT1

MOV A,SBUF

MOV @R1,A

INC R1

DJNZ R0,LOOP

SETB P2.7

LCALL EXCH

RET

EXCH: MOV R1, 30H

MOV A, #00H

CLR C

MOV R7, #08H

LOOP0:XCH A,R1

RRC A

XCH A,R1

RLC A

DJNZ R7,LOOP0

MOV 32H, A

MOV R1, 31H

MOV A, #00H

CLR C

MOV R7, #08H

LOOP1:XCH,A,R1

RRC A

XCH A,R1

RLC A

DJNZ R7,LOOP1

MOV 33H,A

RET