MAX19505 Dual-Channel Analog-to-Digital Converter (ADC)

The MAX19505's analog inputs accept a wide input common-mode voltage range of 0.4V to 1.4V, allowing a wide range of RF, IF, and baseband front ends to be DC-coupled to the inputs. The MAX19505 has excellent dynamic performance over the input frequency range from baseband to over 400MHz, making it ideal for zero-IF (ZIF) and high-IF sampling applications. The typical signal-to-noise ratio (SNR) is 49.8dBFS and the typical spurious-free dynamic range (SFDR) is 69dBc at fIN = 70MHz and fCLK = 65MHz.

The MAX19505 operates from a 1.8V supply. In addition, an internal self-sensing voltage regulator operates from a 2.5V to 3.3V supply (AVDD). The digital output drivers operate from an independent 1.8V to 3.5V supply (OVDD). Analog power consumption is only 43mW per channel at VAVDD = 1.8V. In addition to lower power consumption, the MAX19506 consumes only 1mW in shutdown mode and only 15mW in standby mode.

Access to programmable registers via a 3-wire serial interface enables various adjustments and function selections. In addition, the serial port can be disabled, and three input pins are provided for selecting output mode, data format, and clock division. The data output uses a dual parallel CMOS compatible output data bus, which can be configured as a single multiplexed parallel CMOS bus.

The MAX19505 is available in a small, 7mm x 7mm, 48-pin thin QFN package and is fully specified over the -40°C to +85°C extended temperature range.

Pin- and function-compatible 10-bit 65Msps, 100Msps, and 130Msps devices are available in the MAX19515, MAX19516, and MAX19517 data sheets, respectively. Pin- and function-compatible 8-bit 100Msps and 130Msps devices are available in the MAX19506 and MAX19507 data sheets, respectively.

Key Features

Very low power consumption in operation (43mW/channel at 65Msps)

1.8V or 2.5V to 3.3V analog supply voltage

Excellent dynamic performance

49.8dBFS SNR at 70MHz

SFDR is 69dBc at 70MHz

User-programmable adjustments and function selections via SPI™ interface

Selectable data bus (dual CMOS or single multiplexed CMOS)

DCLK output and programmable data output timing simplify high-speed digital interfaces

Very Wide Input Common-Mode Voltage Range (0.4V to 1.4V)

Very high analog input bandwidth (> 850MHz)

Single-ended or differential analog input

Single-ended or differential clock input

Divide-by-1 (DIV1), Divide-by-2 (DIV2), and Divide-by-4 (DIV4) clock modes

Twos complement, Gray code, and offset binary output data formats

Delimiter indicator (DOR)

CMOS output internal termination option (programmable)

Bit order can be reversed (configurable)

Data output test template

Small, 7mm x 7mm, 48-Pin Thin QFN Package with Exposed Pad