Function and Application of USB Interface Chip FT245BM

Universal Serial Bus (USB) has become an increasingly popular computer communication interface due to its high data transfer rate, ease of use, and support for hot plugging. The FT245BM chip is a second-generation USB interface chip launched by FTDI (Future Technology Devices Intl. Ltd). Compared with other USB chips, the application of the FT245BM chip for USB peripheral development only requires familiarity with microcontroller (MCU) programming and simple VC or VB programming, without having to consider firmware design and driver programming, which can greatly shorten the development cycle of USB peripheral products. In addition, the FT245BM supports USB1.1 and USB2.0 specifications, and the data transmission speed can reach 1M byte/s. Therefore, the FT245BM is an excellent choice for the interface chip required for the development of USB peripherals.

Structure and function of FT245BM

The FT245BM chip is a 32-pin LQFP packaged chip with the following pin definitions:

D[0-7] (25, 24, 23, 22, 21, 20, 19, 18): bidirectional data signal line;

RD# (16): read signal;

WR (15): write signal;

TXE# (14): FIFO transmit buffer empty flag signal;

RXF# (12): FIFO receive buffer non-empty flag signal;

USBDP (7), USBDM (8): USB data signal positive terminal, USB data signal negative terminal;

EECS (32), EESK (1), EEDATA (2): EEPROM chip select line, clock line, data line;

PWREN (10): power enable signal;

SI/MU (11): Immediate send or wake-up signal;

RESET (4): reset signal;

RSTOUT (5): output signal of the internal reset generator; XTIN (27), XTOUT (28): clock input signal, output signal;

TEST (31): test signal;

3V3OUT (6): 3.3V output signal;

VCC (3, 26), VCCIO (13), AVCC (30): chip power, control pin power, internal analog power;

GND (9, 17), AGND (29): chip ground, internal analog ground.

The chip consists of a 3.3V regulator, USB transceiver, phase-locked loop, serial interface engine (SIE), FIFO controller, USB protocol engine, FIFO receive buffer, transmit buffer, 6M oscillator, 8x clock multiplier, etc.

The FT245BM chip can realize the bidirectional conversion of data between the USB interface and the parallel I/O interface. On the one hand, when the USB transceiver receives USB serial data from the host, the serial interface engine converts the data into parallel data and stores it in the FIFO receiving buffer. When the FIFO controller detects that the read signal RD is low, it sends the data in the receiving buffer to the parallel data lines D0-D7. On the other hand, when the FIFO controller detects that the write signal WR is high, it reads parallel data from the data lines D0-D7 and stores it in the FIFO sending buffer. The parallel data is converted into USB serial data by the serial interface engine and then transmitted to the host through the USB transceiver. It can be seen that the FT245BM chip itself can complete the data conversion without the designer considering the hardware design. Its internal structure and function are shown in Figure 1.

Figure 1 FT245BM chip functional block diagram

Hardware interface design

The schematic diagram of the interface circuit is shown in Figure 2.

The design is powered by the USB bus. In Figure 2, the FT245BM is connected to an MCU. An 8-bit port of the MCU is used to transmit data, and the other port is used to control and generate the four handshake signal lines required by the FT245BM, namely RXF#, TXE#, RD#, and WR. When TXE# is low, it means that the current FIFO send buffer is empty. At this time, the WR pulse changes from high to low to write the data on the data lines D0-D7 into the FIFO send buffer; when TXE# changes to high, it means that the current FIFO send buffer is full or is storing the previous byte, and writing data to the send buffer is prohibited. RXF# is low, indicating that there is data in the current FIFO receive buffer. At this time, the RD# pulse changes from low to high, and data will be read from the FIFO receive buffer; when the read signal RD# is low, the data is read to the data lines D0...D7; when RXF# is high, reading data from the FIFO receive buffer is prohibited