【Abstract】 According to the timing analysis of McBSP and CPLD, the CPLD is designed in VHDL language to simulate McBSP and communicate with it in full duplex mode, and the actual interface timing results are given.
Keywords: McBSP, CPLD, VHDL, DSP In many digital signal processing application systems, DSP is responsible for fast and complex core operations. However, the control of DSP on data input and output is limited during the operation. The design combining DSP with CPLD (complex programmable logic device) or FPGA (field programmable array) can effectively make up for this deficiency. The author designed a real-time video codec system based on DSP, which uses the latest high-performance and low-power TMS320VC55x series DSP chip TMS320VC5509 of TI (Texas Instruments) to perform video bidirectional codec operations. However, if DSP also undertakes the work of video input and output, the real-time performance of video codec operations will not be guaranteed. Therefore, Altera's CPLD chip EP1K50 is used as the buffer and control of video input and output. The communication between DSP and CPLD adopts McBSP serial port (multi-channel buffered serial port) DMA mode.
McBSP serial port generally connects data path and control path to external devices through six pins. Data is transmitted through DR and DX pins through McBSP serial port and peripherals, and control synchronization signals are realized by four pins, CLKX, CLKR, FSX, and FSR. Its basic sending and receiving timing is shown in Figure 1. Since the data lines DR and DX of McBSP serial port have cache registers, frame synchronization signals FSX, FSR, and clock signals CLKX, CLKR are programmable, the interface design between it and CPLD is very flexible. The design steps can be: first program CPLD, and then program McBSP serial port according to the waveform characteristics of data sending and receiving, to match the waveform of CPLD.
2 CPLD internal structure design
The data input channel is composed of the video sampling chip SAA7114H, CPLD and the McBSP serial port of C5509. After the video sampling data comes out of SAA7114H, it is buffered in the internal input FIFO (first-in, first-out queue) of CPLD. Since McBSP is serial, parallel-to-serial conversion and serial output must be performed inside CPLD, and a synchronous clock must be generated for the McBSP serial port.
The data output channel is composed of the McBSP serial port, CPLD and LCD (liquid crystal) controller. The decoded video data enters the CPLD serially through the McBSP. After the internal serial-to-parallel conversion, it is sent to the internal output FIFO for temporary buffering, and then enters the external LCD controller.
Reference address：Design of McBSP Interface between CPLD and TMS320VC55x
Keywords: McBSP, CPLD, VHDL, DSP In many digital signal processing application systems, DSP is responsible for fast and complex core operations. However, the control of DSP on data input and output is limited during the operation. The design combining DSP with CPLD (complex programmable logic device) or FPGA (field programmable array) can effectively make up for this deficiency. The author designed a real-time video codec system based on DSP, which uses the latest high-performance and low-power TMS320VC55x series DSP chip TMS320VC5509 of TI (Texas Instruments) to perform video bidirectional codec operations. However, if DSP also undertakes the work of video input and output, the real-time performance of video codec operations will not be guaranteed. Therefore, Altera's CPLD chip EP1K50 is used as the buffer and control of video input and output. The communication between DSP and CPLD adopts McBSP serial port (multi-channel buffered serial port) DMA mode.
1 McBSP hardware interface and timing analysis
TMS320VC5509 is the third generation of high-performance and low-power DSP chip produced by TI. It has three McBSP serial ports. McBSP serial ports are functional extensions based on standard synchronous serial ports, providing a powerful synchronous serial port communication mechanism with a speed of up to 100Mbit/s. It has the following features:
· Full-duplex communication;
· Double-buffered transmit registers and triple-buffered receive registers, allowing continuous data stream transmission;
· Provide independent frame synchronization pulses and clock signals for data transmission and reception;
· Able to send interrupts to the CPU and send event signals to the DMA controller;
· There are 128 channels for transmission and reception respectively, which can allow or block the transmission of a certain channel;
· The data length can be 8, 12, 16, 20, 24, 32;
· Provides A-law and μ-law compression and expansion;
· Programmability of internal clock and frame synchronization signals;
· Direct interface with T1/E1, SPI, AC97, I2S, etc.
2 CPLD internal structure design
The data input channel is composed of the video sampling chip SAA7114H, CPLD and the McBSP serial port of C5509. After the video sampling data comes out of SAA7114H, it is buffered in the internal input FIFO (first-in, first-out queue) of CPLD. Since McBSP is serial, parallel-to-serial conversion and serial output must be performed inside CPLD, and a synchronous clock must be generated for the McBSP serial port.
The data output channel is composed of the McBSP serial port, CPLD and LCD (liquid crystal) controller. The decoded video data enters the CPLD serially through the McBSP. After the internal serial-to-parallel conversion, it is sent to the internal output FIFO for temporary buffering, and then enters the external LCD controller.
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