PCI Express Experimental Development Platform and IP

Since the PCI-E 1.0a specification in 2004, the motherboard has started to have the latest serial high-speed PCI-E bus. Compared with the original PCI V2.3, the PCI-E bus has great advantages. First, PCI-E reduces the number of pins for chip connection and simplifies the design and layout of the PCB board; secondly, PCI-E is a non-shared serial differential interface, and there will be no situation where multiple devices share bandwidth. The theoretical bandwidth of PCI-E x1 is 250M bytes/second for sending and receiving, and the theoretical bandwidth of PCI-E x4 is 1G bytes/second for sending and receiving. In addition, the PCI-E 2.0 protocol will use a higher-speed physical layer transceiver of 5G BPS, which will double the speed. Therefore, the PCI-E bus interface is particularly suitable for ultra-high-speed data transmission, and will replace the PCI interface within 3 years. Based on this situation, our company has launched the S2300 PCI-E interface FPGA development experimental platform to meet the needs of the market and meet the needs of users for high-speed data transmission.

The development experiment board adopts PCI-E x1 interface and provides 80 available FPGA IO inputs and outputs to facilitate users to carry out independent development. Users can design application plug-in boards by themselves, such as external A/D data acquisition, image data processing and other system applications, without having too much knowledge of PCI-E interface.

The PCI-E interface chip uses PLX8111BB66BC from PLX, which fully supports PCI-E 1.0A protocol. The external interface supports a maximum operating frequency of 66M, a 32-bit bus width, and a maximum burst peak transfer speed of 266M bytes/second.

The core FPGA chip uses ALTERA's new CYCLONE FPGA series, EP1C12Q240C8, with a capacity of 12,000 logic macro units, equivalent to a standard 300,000 logic gate circuit, and a speed of -8. After compilation, the system speed can reach 100MHz, which can support the development of ALTERA's SOPC core NIOS2 system. The executable file compiled by the NIOS2 development environment can be downloaded to the FLASH on the development board through the PCI interface.

PCI-E development board photo

Performance parameters:

The FPGA's external bus interface supports 8, 16, 32, and 64-bit data buses and can directly communicate with CPU, SDRAM, FIFO,

SRAM, external interface chips and other devices are directly connected.

The following is the internal IP core interface of the FPGA development board:

PCI bus 2.3 standard, 32-bit bus, complete VHDL source code design provided;

Support PCI 66M bus operating frequency standard;

Support PCI bus configuration read and configuration write;

Support PCI bus IO read and IO write;

Support PCI bus BUS MASTER read, BUS MASTER write;

Support internal DMA interrupt and external bus input interrupt generation;

Supports one PCI IO space with a size of 256 bytes;

Supports a PCI memory space with a size of 4M bytes;

Support PCI burst access mode, burst length is 8 to 128 double words;

Users can define their own device ID and manufacturer ID;

1 FPGA internal 16C450 serial port, fully provided by VHDL core;

1 group of 4MX32-bit SDRAM, the capacity supports up to 64MX32-bit SDRAM interface, full VHDL core SDRAM interface

Source code provided;

1 set of 16-bit FLASH (29LV800BB), 1M bytes, can be expanded to 32 bits, up to 16M bytes FLASH, full VHDL

Source code design provided;

4-channel switch output, open collector output, 500ma drive current, expandable to 64 switch outputs;

4-channel switch input, expandable to 64 inputs;

4 LED status indicator outputs for debugging and testing, complete VHDL kernel source code provided;

Externally expand the standard 32-bit data bus to provide DMA data transmission capability;

Through the 2.54MM 100-pin connector, it provides 80 GPIO inputs and outputs, and users can design various A/D boards by themselves.

When plugged into the development platform, the operating frequency of the external bus interface can reach 66MHz;

All the above functions are accessed and operated through PCI interface, and WDM driver and test software for WINDOWS2000/XP are provided.

The test program can test the functions and performance of the SDRAM and FLASH interfaces of the development platform.

able.

The S2300 Development Platform Kit includes:

One S2300 PCI-E x1 development platform hardware circuit board;

An ALTERA BYTEBLASTER2 download cable;

ALTERA QUARTUS2 4.1 development platform installation CD;

WIN2K/XP DDK and DRIVERWORKS driver development tools

CD;

FPGA internal full source code design and user manual and instructions;

The driver has complete source code design and user manual and instructions;

PCI-E circuit design documentation;

S2300 circuit schematic and PCB library design;

Applications:

Industrial data acquisition, a/d, d/a data conversion, data processing;

Multi-channel 232/485 expansion, no need for external 16c550, 1C6 can provide up to 12 serial ports,

The internal 16c550 fifo can reach 1k bytes;

Multi-channel switch input/output expansion, expandable to 64 channels;

pci data buffer, data encryption;

Industrial Control ;

And other user-customized designs;