Soft Error Rate (SER) Issues of Memory Data

The soft error rate (SER) problem first gained widespread attention as a memory data topic in the late 1970s, when DRAMs began to show signs of random failure. As process geometries continued to shrink, the critical charge required to cause a mismatch decreased much faster than the charge accumulation area in the memory cell. This meant that: When using smaller process geometries such as 90nm, soft errors became a more significant concern and further steps were taken to ensure that the soft error rate was maintained at an acceptable level.

SER's Tendencies and Implications

The compression of process size has become the main tool for achieving industry survival, and it plays an important role in increasing density, improving performance and reducing costs. As device processing technology moves towards deep submicron gate signal width (0.25mm→90nm?), the cell size of memory products continues to shrink, resulting in lower and lower voltages (5V→3.3V→1.8V...) and a reduction in the internal capacitance of the memory cell (10fF→5fF...). Due to the reduction in capacitance, the critical charge in the memory device (the minimum charge required for a memory cell to store data) continues to shrink, thus reducing their natural resistance to SER. This in turn means that alpha particles or cosmic rays with much lower energy are likely to interfere with the memory cell.

System-level implications and importance

Soft errors are measured in FITs. The FIT rate is simply the number of failures that occur in 1 billion device operating hours. 1000 FITs corresponds to an MTTF (mean time to failure) of about 144 years. To understand the importance of soft errors, let's look at some examples of their potential impact in typical memory applications. For example, a cell phone using a 4Mbit low-power memory with a soft error rate of 1000 FIT/Mbit will likely experience a soft error every 28 years. A standard high-end router using 100Gbits of synchronous SRAM with a soft error rate of 600 FIT/Mbit is likely to experience an error every 17 hours. Soft errors are also important because their FIT rate is currently more than 10 times the typical FIT rate for hard reliability failures. Obviously, soft errors are not a big deal for a cell phone, but systems using large amounts of memory can be severely impacted.

The roots of SER

Now that you have a general idea of ​​soft errors, let’s briefly discuss the mechanisms that cause the different root causes of soft errors one by one.

Effects of alpha particles

The molding compound used in semiconductor device packaging may contain impurities such as Th232 and U238, which tend to decay over time. These impurities release alpha particles with an energy range of 2"9MeV (million electron volts). In silicon material, the energy required to form an electron-hole pair is 3.6eV. This means that alpha particles may generate about 106 electron-hole pairs. The electric field in the depletion region will cause charge drift, causing the transistor to experience current disturbances. If the amount of charge transfer exceeds the critical charge (QCRIT) stored in the memory cell in the 0 or 1 state, the stored data will flip.

The impact of cosmic rays

High-energy cosmic rays and solar particles react with the upper atmosphere. When this happens, high-energy protons and neutrons are produced. Neutrons are particularly difficult to deal with because they can penetrate most man-made structures (for example, a neutron can easily penetrate 5 feet of concrete). The strength of this effect varies with latitude and altitude. In London, the effect is 1.2 times stronger than at the equator. In Denver, due to its high altitude, the effect is three times stronger than in San Francisco at sea level. And on an airplane, the effect will be 100-800 times stronger than on the ground.

High energy neutrons have energies in the 10"800 MeV range and, because they have no charge, react differently to silicon than alpha particles do. In fact, the neutrons must bombard silicon nuclei to cause soft errors. This collision has the potential to produce alpha particles and other heavier ions, which can generate electron-hole pairs, but these electron-hole pairs have higher energies than typical alpha particles from the molding compound.

Effects of thermal neutrons

Thermal neutrons can be a major source of soft failures, and they generally have very low energy (about 25 meV). These low energy neutrons are easily captured by the B10 isotope that is present in large quantities in the BPSG (boron phosphosilicate glass) dielectric layer. The captured neutron will result in a fissioned lithium, an alpha particle, and a gamma ray. Thermal neutrons are only a problem in the presence of BPSG. So this effect of thermal neutrons on SER can be offset by completely abandoning the use of B10. Table 1 compares the sources of soft errors.

Measurement technology

There are several ways to measure the sensitivity of a device to soft errors. One method is to accelerate the measurement, and another method involves system-level measurement. The geographical location of the test site has a great impact on the final data obtained. In order to minimize the difference in measurement data between different companies and maintain a common reference point between different product vendors, the industry standard is for all vendors to publish their SER FIT rate adjusted to the New York City/sea level location.

There are two methods for measuring accelerated SER data: alpha particle acceleration testing and cosmic ray acceleration testing. The sensitivity of a device to alpha particles can be determined by placing a thorium or uranium ion source on a decapped chip and measuring the total number of misalignments in a specific time and inferring the Fit/Mbits method.

The two accelerated data measurements described above are a reasonable approximation of the FIT rate, but tend to overstate the actual failure rate. The accelerated data can be used as a good approximation of the total time required to calculate a system SER measurement.

On the other hand, system SER measurement requires placing thousands of devices on a circuit board and continuously monitoring the system to measure the total amount of misalignment that occurs. System SER is the accumulation of alpha and cosmic ray SERs, and this data is highly dependent on the geographic location of the system. One good way to eliminate the alpha-cosmic ray effect in a system is to measure the data while placing the system several meters underground (where the effect of cosmic rays is negligible) and then monitor the system at high altitude (where the effect of alpha particles is completely negligible).

System soft error rate measurements are quite expensive and are often performed by memory vendors at the technology (rather than device) level in order to reduce costs.

Inhibition of SER

Methods to reduce SER can be divided into several categories, including process changes (buried layer, triple well, etc.), circuit enhancement (resistive feedback, setting higher capacitance on the storage node, higher drive voltage, etc.), design enhancement (redundancy, etc.) and system-level changes.

System-level countermeasures

At the system level, error detection and correction can be performed based on read operations, and the SER rise of the SRAM can be suppressed by slightly increasing the delay (wait time) of the SRAM. This allows single-bit error correction of data and reporting of multi-bit errors. Some improvements can also be achieved through system and memory architecture design. The memory topology bitmap can be constructed in a way that an actual multi-bit event causes a multi-bit or single-bit error in a byte. ECC is very effective in correcting single-bit errors, but its use also means that the chip area will increase by at least 20%.

Device process/packaging level countermeasures

From the perspective of device design, one way to suppress SER and enhance the device's resistance to SER is to increase the critical charge stored in the memory cell. It has been noted that the PMOS threshold voltage can reduce the recovery time of the memory cell, which indirectly plays a role in improving SER resistance. In addition, the charge generated during the soft error can be dissipated using a buried node (triple well architecture) to increase recombination away from the radioactive area. This will generate an electric field in the opposite direction of the NMOS depletion layer and force the charge into the substrate. However, this triple well architecture can only play a certain remedial role when the radiation occurs in the NMOS region.

Conclusion

As the process size continues to shrink, the impact of "soft" errors on memory devices has evolved from "insignificant" to an important issue that needs to be carefully considered in system design. SRAM vendors such as Cypress have taken corresponding countermeasures in process development and product design to minimize the device's sensitivity to SER, thereby expanding the application range of SRAM to process geometries far less than 90nm. With the right countermeasures at the system design and product design levels, SRAM will continue to be a viable memory solution for multiple generations of processes.