Application of Farad Capacitor in RAM Data Protection

Farad capacitors are also called supercapacitors and double-layer capacitors. They are small in size, large in capacity, have good voltage memory characteristics, and are highly reliable. Compared with rechargeable batteries, they have the advantages of short charging time, high power density, long service life, good low-temperature characteristics, and no environmental pollution [2]. Using farad capacitors to replace batteries as backup power sources in data protection circuits is of great significance in improving system reliability, extending service life, and reducing equipment costs and maintenance costs.

This article will use a design case to specifically introduce the application of farad capacitors in RAM data protection in microcontroller systems, providing a feasible reference method for RAM data protection in embedded systems.

A single-chip computer system that uses UT6264C70LL as RAM requires the RAM data backup time to reach 5 days after the system power fails.

1 Hardware Design

Using a farad capacitor as the RAM backup power supply, the typical calculation formula for the farad capacitor backup time is:

Where: C(F) is the nominal capacity of the Farad capacitor, Uwork(V) is the normal working voltage in the circuit, Umin(V) is the minimum working voltage of the circuit, t(s) is the backup time in the circuit, and I(A) is the load current of the circuit.

The typical data retention current of UT6264CSC70LL is 1 μA, the operating voltage is 5 V, and the minimum voltage required for data retention is 2 V. Taking a 0.1 F capacitor, the data backup time of the RAM is calculated to be 3.35 days. In fact, when the power supply voltage of the RAM is reduced, its data retention current will decrease, so the backup time can be extended.

In addition, when the power supply fluctuates, the chip select pin, write enable pin and data line port of the RAM are also prone to introduce interference or abnormal control timing, thereby destroying the data in the RAM. Therefore, it is necessary to ensure that the timing of the read and write control ports can be controlled when the power supply is abnormal through circuit design, thereby enhancing the security of RAM data.

The circuit schematic is shown in Figure 1.

When the power supply is normal, the 5 V power supply VCC supplies power to RAM (U2: UT6264) through the fast rectifier diode D1, and charges the farad capacitor (C1: FM0H104Z) through R1. When the power is off, D1 is cut off, and the farad capacitor C1 serves as a backup power supply, supplying power to U2 through R1 to ensure that the data in the RAM does not disappear.

In order to enhance the security of RAM data during power-off or power fluctuation, a dedicated power monitoring chip (U3: IMP706) is used to provide system monitoring functions. A reset signal will be output when power is on, power is off, and the grid voltage is too low. At the same time, it can track the 1.6 s timing signal to provide watchdog timer protection for software operation. When the power supply voltage drops to about 4.74 V, U3 outputs a power-off signal (PW_DN) to the CPU (U1: AT89S52), and the CPU performs power-off emergency processing and protects the site, and does not perform any read or write operations on the RAM chip. When the power supply voltage further drops to 4.4 V, U3 generates a reset signal, the CPU is reset, and the chip select pin CE2 of the RAM chip U2 is also set to a low level to ensure that U2 is not read or written.

Figure 1 Circuit diagram

2 Software Design

The address definition of the circuit in this case is: the RAM address range (8 KB) is 0000H~1FFFH; the watchdog timer control address is E000H.

The software includes main control program, power-off interrupt processing program, timer interrupt processing program, etc.

Figure 2 Main process

(1) Main control program

After powering on and performing necessary CPU initialization, the normal power-off flag and RAM Check Sum calculation check are checked to confirm whether the data in the RAM is normal. If normal, the on-site recovery before power failure is performed. The main program flow chart is shown in Figure 2.

(2) Power-off interrupt handler

When the CPU receives the power-off signal (PW_DN) interrupt, the CPU performs power-off emergency processing and protects the scene, sets the normal power-off flag, and saves the RAM Check Sum calculation result to check whether the RAM data is damaged when power is turned on. The flow chart is shown in Figure 3.

Figure 3 Power-off interrupt processing flow

Figure 4 Timer interrupt processing flow

(3) Timer interrupt handler

The watchdog timer circuit needs to be cleared every 1.6 seconds, and the watchdog clearing subroutine is called in the timer interrupt handler. The timer interrupt time should be set within 1.6 seconds, for example, 100 ms. The flowchart of the timer interrupt processing is shown in Figure 4.

Conclusion

In this application example, after testing, the RAM data backup time after power failure is 10 to 14 days, and the data is reliable and the system runs stably. Obviously, choosing a larger value of Farad capacitor will have a longer backup time. In the product design of the control system, in order to improve product reliability, reduce costs, and enhance product competitiveness in the market, the solution provided in this article has reference value.