Design and verify synthesizable analog and RF models for complex SoCs

Design and verify synthesizable analog and RF models for complex SoCs

Designing complex analog and RF modules for SoC integration is a daunting task. This article describes a method for optimizing designs based on performance metrics specifications (such as PLLs or ADCs) to ensure a robust design for manufacturability. With such a design, developers can bring products or devices to market efficiently and on time while ensuring cost-effectiveness and staying within budget.

For today's complex system-on-chip (SoC) designs, especially those containing complex modules such as PLLs or ADCs, designers can gain the following benefits by using a comprehensive platform: 1) they can create an optimal module design based on performance specifications; 2) they can evaluate the trade-off between performance and design margin (e.g., between chip area and speed);

When the user inputs the performance index specification, the synthesis platform can optimize the device size and layout and routing synthesis at the same time by expressing the circuit formula as a convex optimization problem. In this way, the challenge for the designer is only to verify through synthesis whether the synthesized design is correct and whether it can meet the expected performance requirements under all working conditions, without having to perform detailed silicon verification for each example.

We all know that designers are under tremendous pressure to reduce chip size while maximizing functionality and minimizing power consumption. As a result, the reliability margin is reduced, making the manufacture of robust analog and RF ICs a difficult task. The following factors need to be paid attention to:

1. Circuit performance depends primarily on the behavior of transistors;

Small changes in the manufacturing process can lead to large changes in circuit performance. During production, changing technical parameters can cause circuit failure. The goal of design for manufacturability is to design so that most manufactured circuits meet performance specifications while minimizing area overhead. This requires the use of accurate transistor models for different processes.

2. Background noise coupling due to fast switching digital circuits, for example, can significantly degrade the quality of sensitive analog signals;

Therefore, designers must perform careful layout design to reduce device mismatch and parasitic effects, which is critical to ensure correct circuit behavior. Unlike digital circuits, analog circuits require designers to keep in mind a large number of performance specifications, so redesigning analog blocks is a very time-consuming task. For designs using 0.13 micron processes and below, HCE, NBTI, and STI stress effects must be met to achieve optimal analog and RF performance. In the face of these challenges, existing commercial tools designed to control reliability targets are not accurate.

How to verify robustness?

Designers can achieve robust designs by considering various factors that adversely affect manufacturing yield and performance and incorporating them into a comprehensive platform.

Designers can also include multiple technology variations in the same equations that describe circuit behavior and performance specifications. If boundary design is feasible, it means that as long as the design is within the feasible range, there is no need to verify each new instance.

A traditional strategy for improving yield is to run multiple Monte Carlo simulations, but Monte Carlo analysis is a painstaking process to ensure yield optimization.

Monte Carlo analysis creates a collection of circuits with components of varying tolerances and statistically tests the circuit performance. Each circuit is constructed from a number of components randomly selected from a large collection of components that match the user-defined tolerances and distribution type. The result is a design constraint distribution curve. From this data, reliability, cost, and the ability to manufacture the circuit can be analyzed. The concept is to use multiple Monte Carlo simulations in an optimization procedure.

The loop consists of an optimizer recommending a candidate circuit, and then an evaluation engine evaluating the quality of each candidate circuit. This cycle repeats until the specifications are met. This process is called a design-centric approach and can only be used for post-design optimization. Some commercial tools use SPICE and one or a set of numerical search engines. The optimizer can be: a design engineer; simulated annealing; Newton's method; or any other type of classical optimization method.

Needless to say, the Monte Carlo method is a CPU-intensive method that is not practical for circuit designs with more than a few dozen transistors. More importantly, the method requires the work of both analog circuit designers and optimization experts: the SPICE architecture and test bench are input by experienced analog designers, and the step size, search space, and search method are selected by the optimization expert. In short, the Monte Carlo method requires expert resource planning and is extremely time-consuming, all of which make it necessary to have a new method for optimizing yield.

Bump Optimization

The transistor behavior and performance indicators of analog and RF components (such as phase-locked loops and data converters) can be expressed as polynomials of design variables. (See Figure 2)

If the designer expresses his design problem as a geometric program, he can create a special type of convex optimization problem. The final solution is completely independent of the starting point (even if the starting point is infeasible and the infeasibility indicator can be clearly detected). The designer can benefit from a very efficient global optimization method, which can obtain a very fast result even for large problems. If such a solution exists, the program is guaranteed to converge. In fact, it is a fast synthesis method that can determine the globally optimal design.

By changing the variables and considering the signs in the relevant functions, the geometric program can be reformulated as a convex optimization problem. When modeling circuits using geometric programs, the design space is represented as a convex set, and convex problems have a special property: their feasible sets are convex.

Robust analog circuit creation

As we know, statistical variations in electrical parameters (such as transistor gain, etc.) are caused by variations in the manufacturing process and can affect circuit performance and yield. By ensuring tight coupling between manufacturing and circuit design, the synthesis platform can produce robust designs.

These process variations are due to random manufacturing variations and are traditionally incorporated into process models. For example, non-uniform conditions in dopant diffusion or deposition during device manufacturing can lead to variations in oxide thickness and diffusion depth. Variations in oxide thickness and doping levels in substrate, polymerization, implantation, and surface charge can affect threshold voltage values. Resolution in photolithography processes can cause W/L variations in MOS transistors. These parameter changes can in turn cause changes in electrical parameters such as sheet resistance and threshold voltage.

For example, an op amp is constrained to a specific power consumption with a 500 MHz unity gain bandwidth. To meet this constraint, the design can be optimized at multiple process stages and can also include supply voltage variations and factors such as resistor variations. Table 1 lists some of the process-dependent metrics that are included in the synthesis platform as part of the optimization procedure.

Now let's explain the parameters listed in Table 1. The percentage variation of the supply voltage can be set, for example, to 10%. On a 1.8 V supply, optimization can ensure that all specifications are achieved at 1.62 V and 1.98 V (that is, Vdd ± 10%). For example, when the power consumption is worst-case at 1.98 V, the saturation margin will be worst-case at 1.62 V. If the percentage variation of any on-chip resistor is 20%, then optimization can ensure that all specifications are achieved at ± 20% resistor values. Since resistors can be used in voltage reference and loop filtering circuits and thus have a significant impact on manufacturing yield, the reference current variation and its stability margin will be considered during optimization.

When selecting the process stage for robust design, the following requirements should be followed:

Each process stage must be able to maintain each indicator, and the reported indicator value is the worst value of the selected stage;

? The reported value for the target should be the worst value over all phases.

Parameter Matching

In addition to process variations between wafer lots, analog designers must pay close attention to device performance because device performance can vary between devices on the same chip.

Transistor and circuit mismatches have a significant impact on the performance limits of analog designs. Typical performance parameters such as data converter resolution, op amp CMRR and PSRR all depend on transistor matching. These matching (or mismatch) effects can severely affect the robustness of a design.

The designer can use the mismatch in transistor threshold voltages to calculate the noise component of the design. He can model this mismatch either as a variation of the threshold voltage for a specific transistor and the nominal threshold voltage for the process, or as a random variable with a deviation inversely proportional to the device area. He can model the standard current deviation as a percentage variation between the saturation current Id,sat of a specific transistor and the nominal saturation current Id,sat of the transistor in the process. Due to random variations in the manufacturing process, the transistors on either side of the differential pair will show a mismatch in threshold voltage and saturation current.

Noise and power supply variations

Factors such as noise and power supply voltage variation have a much greater impact on analog and RF design than on digital design. For example, primary parameters such as gain and bandwidth in analog design can be well met. However, due to noise, indicators such as SNR cannot be well achieved.

The optimized design must not only be robust in a noisy environment, but also be resistant to power supply variations. To meet these constraints, the synthesis platform allows the user to tune the design for any environment. The following illustrates an example of using the accumulated power supply jitter (10% step on Vdd) in the PLL to resist power supply voltage variations.

When such a step is applied, the instantaneous phase error between the ideal reference clock and the output clock will begin to accumulate. After a period of time, the loop will react and start driving these signals back into phase adjustment. This specification represents the worst instantaneous phase error after the voltage step. For robustness, it is assumed that the rise time of the voltage step is much smaller than the reference period. In reality, any on-chip voltage step will most likely have much shorter rise and fall times and therefore provide much better performance than this specification.

The design may be more vulnerable to one type of noise than another. The solution is for the user to evaluate the environment and identify the biggest weakness, then set the constraint to a low value, identify the next biggest weakness and set it to a slightly higher value. The optimizer attempts to match all constraints, and setting the most important constraint to the tightest value and the least important constraint to the loosest value allows the optimizer to best meet the design requirements.

parasitic

Designers using the synthesis platform can also include all parasitic effects at the beginning of the optimization and eliminate uncertainty in the design process by building them into the optimization models. These models are built to handle signal integrity issues such as unwanted resistance, capacitance and inductance effects associated with devices and their interconnections. Designers can model effects such as mutual coupling between adjacent wires, and if these factors affect performance, the program algorithms in the synthesis platform will take these factors into account in the circuit layout.

Layout and Routing

The synthesis platform uses geometric programs to control circuit layout to achieve system performance goals. These issues involve devices, modules, bottom-level planning and routing. In order to achieve the performance indicators required for analog and RF circuits, the following circuit layout and routing constraints can be considered.

Symmetrical constraints: A component can be constrained to be centered on a horizontal or vertical axis; two components of the same size can be constrained to be mirrored relative to the axis.

Mirror Nodes: Nodes can be mirrored around an axis.

Node Matching: Markers (layout extensions) can be added to the routing so that the horizontal and vertical metal lengths between two nodes are generally balanced.

Alignment: Two components can be constrained to align with each other along the top, bottom, left, or right.

Capacitance constraint: This can be used to limit the capacitance between the trace and the substrate by bending the trace length.

IR Drop Constraint: The router will size the power tracks to limit the IR drop value to a specified value.

Another important consideration in the device generator is intermediate digitization, which reduces device capacitance and ensures symmetrical current directions, guard rings, dummy structures, etc. Figure 3 shows an example of a device generated for an analog or RF design.

How to Verify the Robustness of Analog Designs

Barcelona ensures that the robustness of each optimization case is verified by using a verification pyramid, which has been applied to 0.18 and 0.13 mm synthesis platforms. As I mentioned earlier, using this verification pyramid allows us to avoid the pain of setting up and running Monte Carlo simulations, as well as the cost of running multiple silicon manufacturing processes.

Our verification pyramid is divided into 4 levels. Level 1: We first select the specifications based on experiments and heuristic design. The design specification space is covered by uncorrelated sweeps of the main indicators. In the case of PLL, these are jitter, power and static phase error. We use heuristic criteria for the definition of a grid that takes into account the correlation of the indicators.

We performed a series of optimizations to qualify the functionality of this synthesis platform. This process included increasing the number of test scenarios from 3 to 49. The test scenarios were defined to select process stages from 1 to 7, vary the power supply by 10% from its nominal value, vary the on-chip polysilicon resistance by 20% from its nominal value, and select three VCO frequencies.

Level 2: We verify the accuracy and functionality of the optimized design from level 1 by checking the correlation between the parameters that can be extracted from SPICE simulations and the parameters predicted from the synthesis platform.

We place special emphasis on SPICE simulation of analog circuit blocks. For example, for the VCO, we simulate the following at both low and high frequencies: power saturation margin, frequency range, kVCO gain, PSRR, (kVdd).

Level 3: We seek to provide correlations between the metrics predicted by the synthetic platform and the extracted simulations at the macro level.

To ensure that the specifications are ready for manufacturing, we require that the synthesis platform can generate GDSII data with no layout and schematic errors. We also require that no semiconductor design rules be violated.

One of the main problems in analog design that can degrade performance or even cause the design to fail is parasitics.

Tier 3 verification includes parasitic prediction for automated GDSII layout. Tier 2 selection is based on frequency coverage and low jitter range, low power PLLs and is performed for the corresponding frequency range and silicon samples covering the following applications: consumer multimedia, wireless and wired communications, microprocessors and ASICs.

Tier 4: The final step in comprehensive platform verification is silicon validation. The goal here is to confirm the stringency and robustness of Tier 1 through three qualification tests in silicon. A Tier 3 design was selected. Tables 2 and 3 show the key parameters of two PLLs produced on TSMC’s 0.18 μm logic process. Results are shown for worst-case process, voltage, and temperature variations. A GDSII layout can be generated in a matter of hours and can be submitted directly to the foundry without any changes.