DS1870 Lookup Table Structure

Abstract: This application note describes the control path from input to output of the DS1870 LDMOS RF power amplifier bias controller and discusses the internal calibration process.

Overview

This application note illustrates how to use the 2D lookup table of the DS1870, which is used to bias an RF power amplifier.

Input to output path

Figure 1 shows the path from the sense input to the output setting of the potentiometer wiper position.


Figure 1.

All inputs are single-ended inputs referenced to ground. Two very important signals in this example are ID1 and the on-chip temperature sensor. These analog signals are fed through a multiplexer into the programmable gain stage on the analog side of the A/D converter (ADC). After quantization by the ADC, the offset calibration is applied to the digital portion of the ADC. The following calibration process allows the gain and offset calibration (scaling) to be programmed. Each signal has its own gain and offset scaling coefficient. The values ​​obtained so far can be used as index pointers into a two-dimensional lookup table, one table indexed by temperature and the other table indexed by ID1. As the pointer moves from one position to another, the contents of the corresponding register are fed into an accumulator via the bus. The accumulator sums the values ​​of the two registers at the time corresponding to the change in temperature and ID1. The sum represents the position of the center wiper of the potentiometer.

Note: ID1 can be any voltage signal, representing current, external temperature, or any other variable.

Scaling and calibration

During calibration, each signal is scaled by setting the gain and offset, so that ID1, ID2, VD, ... can be adjusted individually, whether they are below 250mV or above 2.5V, to optimize the use of the A/D converter.

The calibration of the input variables is explained in detail on page 12 of the data sheet, "Voltage Monitor Calibration", and further explained in this article. In essence, it is a repeated 2-point calibration (low, high, low, high), and at each point (low analog input/low digital output, high analog input/high digital output), each bit of the scale (gain) register (register in Table 1 on page 17) is adjusted by subsequent quantization.

The process is: Set the offset register to 0h >>> Start loop {set analog input to 0, read quantized value Meas1 >>> Set analog input to 0.225 (FS = 0.25 in the example),

read quantized value Meas2 >>> If (Meas2 - Meas1) > desired difference: CNT2 - CNT1,

then the MSB of the scale register is 0, otherwise it is 1 } >>> Repeat the next loop until all bits in the scale register are set.

After the last bit is set, set the input to 0 and set the offset register.

Note: It is not necessary to set the analog input to 0 in the above operation, it is the "real" minimum value of the measured parameter (current, temperature). The desired difference represents the difference (CNT2 - CNT1) you want to adjust the digital scaling ratio, given a 90° full-scale analog input difference. Unless you are limited by a certain monitored quantity, you can choose the slope to cover the widest range, which will make your LUT control work best (refer to Table 6 and the notes for the maximum value FE00h for the VD channel and 7E00h for the ID1 and ID2 channels). For example, if you know that the current will not exceed 2A, you can set the expected difference to 7166h (7E00h × 0.9), which represents 1.8A (2 × 0.9).