Realization of Phase-locked Frequency Multiplication Circuit in Active Power Filter

Realization of Phase-locked Frequency Multiplication Circuit in Active Power Filter

Active Power Filter (APF) is a power electronic device that dynamically suppresses harmonics and compensates reactive power. The phase-locked frequency multiplier circuit is an important component of the harmonic detection module of the active power filter. Its stability plays a key role in the rapid response of the active power filter. The signal frequency of the power supply system varies in a large range with the change of load. In order to achieve accurate signal sampling, the DSP must accurately know the frequency of the current signal to ensure that the sampling frequency is consistent with the signal frequency. The phase-locked frequency multiplier circuit divides a complete cycle into N equal parts as the sampling signal of the DSP.

1 Principle of Phase-locked Frequency Multiplication Circuit

Whether the phase-locked frequency multiplication circuit can output a 12.8kHz square wave in real time and stably is the key to whether the entire detection module can start working in the shortest time after being turned on. Figure 1 shows the principle block diagram of the phase-locked frequency multiplication circuit.

Figure 1 Principle block diagram of phase-locked frequency multiplication circuit

As can be seen from Figure 1, the phase-locked frequency multiplication circuit is a closed-loop frequency feedback system, which is mainly composed of a phase detector, a low-pass filter, a voltage-controlled oscillator and an accumulative counter.

A phase detector is a circuit that makes the output voltage have a definite relationship with the phase difference between two input signals. It is one of the basic components of a phase-locked loop (PLL). Phase detectors can be divided into analog phase detectors and digital phase detectors.

The output signal of the phase detector contains many harmonic components. When the phase-locked loop is in a locked state, the first item of these components is the "DC" component, and the other frequency components are unnecessary signals. In addition, in the signal transmission of the phase-locked frequency multiplication circuit, there will also be high-frequency noise that interferes with the signal. These higher frequency components are also unnecessary signals, so they must be filtered out with a low-pass filter. In this design, a first-order low-pass filter is used.

A voltage-controlled oscillator (VCO) is an oscillation circuit whose output frequency corresponds to the input voltage. In the automatic frequency control loop and the phase-locked loop, the input control voltage is the error signal voltage, and the voltage-controlled oscillator is a controlled component in the loop.

In the APF detection system, the output of the phase-locked frequency multiplication circuit is used as the signal to start AD sampling. The divider divides the output signal frequency generated by the VCO by N. This factor is variable or programmable in most cases. The divider is usually composed of a cascade of triggers (such as RS triggers, JK triggers, or T triggers). One JK trigger can divide the clock input signal added to it by 2, two can divide it by 4, and so on.

In this circuit, a binary adder counter CD4040 is used, that is, its accumulated numbers are all multiples of 2. If you want to get 256 times, the output signal is output from its Q8 pin.

2 Design of Phase-locked Frequency Multiplication Circuit

2.1 Zero-crossing detection circuit

The schematic diagram of the zero-crossing detection circuit is shown in Figure 2. The circuit uses the Yubo CHV-25P Hall voltage sensor, which has a rated current of 10mA and a primary-to-secondary turns ratio of 2500:1000. Therefore, before connecting the A-phase grid voltage to the Hall voltage sensor, a current limiting resistor is required to limit the current to prevent the Hall voltage sensor from being burned out by excessive current. Its M terminal is the secondary current output terminal, and a sampling resistor is required to introduce the voltage drop on the resistor into a hysteresis comparator composed of an operational amplifier CA3140 and four resistors. Then, after passing through a clamping circuit composed of two diodes at its output terminal, the high and low levels are locked to 5V and 0V, and then enter a NAND gate CD4093 to shape the output signal and convert the signal into a standard square wave with a high level of 5V and a low level of 0V. This square wave will then be used as the input signal of the phase-locked frequency multiplication circuit.

Figure 2 Schematic diagram of zero-crossing detection circuit

2.2 Phase-locked frequency multiplication circuit

This phase-locked frequency multiplication circuit uses a phase-locked loop chip 74HC4046, an accumulative counter CD4040 and a low-pass filter. The circuit connection diagram is shown in Figure 3.

Figure 3 Schematic diagram of phase-locked frequency multiplication circuit

After the A-phase voltage passes through the zero signal detection circuit, a 50Hz square wave synchronized with the A-phase voltage is obtained. As the input signal of the phase-locked frequency multiplication circuit, it enters the No. 14 pin of the phase-locked loop chip 74HC4046. The No. 4 pin is the output end of the voltage-controlled oscillator inside the 74HC4046. Its output signal is input to the No. 10 pin of CD4040 for 256 times frequency multiplication. Its frequency multiplication signal is output from the No. 13 pin of the binary counter CD4040 and enters the No. 3 pin of the 74HC4046, i.e., the comparison signal input end. After the internal phase comparator of the 74HC4046 compares the phases of the two signals, the signals are input from the No. 13 pin of the output end of the phase comparator II. After the high-frequency noise is filtered out by the low-pass filter composed of , and , the high-frequency noise is filtered out and then enters the internal voltage-controlled oscillator of the 74HC4046 as its control signal. From the above process, it can be seen that this is a closed-loop control system. After continuous adjustment, the frequency of the output signal is 256 times the frequency of the input signal, and the frequency difference between the input signal and the comparison signal is zero.

3 Experimental results and analysis

The experimental waveform of the zero-crossing detection circuit when the external signal frequency is a 50Hz sine wave is shown in Figure 4.

Figure 4 Zero-crossing signal and sine waveform

FIG5 shows the output experimental waveform of the designed phase-locked frequency multiplication circuit.

Figure 5 12.82kHz square wave output by phase-locked frequency multiplication circuit

The input voltage of the voltage-controlled oscillator comes from the output of the low-pass filter, so the output frequency will fluctuate to a certain extent. The output frequency range of this phase-locked frequency multiplier circuit is 12.77kHz-12.82kHz. After the frequency output by the phase-locked frequency multiplier circuit is captured by the DSP, AD7656 will be started to sample the signal. Due to the pulsation of the output frequency, the sine and cosine values ​​of the sampling point may have a certain error with the sine and cosine table stored in the table. Under the premise of meeting the phase-locked speed, the cutoff frequency of the low-pass filter should be reduced as much as possible to reduce the fluctuation of the output frequency.