Logic Analyzer Principle and Application

When you need to view the input and output signals of a 16-bit counter simultaneously to identify timing errors, choosing the wrong tool can be time-consuming. Using a logic analyzer is the best solution to this problem. This article will detail the basic principles of a logic analyzer and its functions.

Keywords: logic analyzer; sampling; triggering

introduction

Generally speaking, a logic analyzer can see more signal lines than an oscilloscope. A logic analyzer is particularly useful for observing timing relationships or data on a bus - such as a microprocessor address, data, or control bus. A logic analyzer can decode the microprocessor's bus information and display it in a meaningful form. In short, when you pass the parametric design stage and start to care about the timing relationships between many signals and need to trigger on logic high and low level patterns, a logic analyzer is the right test tool.

Logic Analyzer

Most logic analyzers are actually two analyzers in one: one part is a timing analyzer, the other part is a state analyzer.
A timing analyzer displays information in the same format as an oscilloscope, with time on the horizontal axis and voltage amplitude on the vertical axis. Because the waveforms on both instruments are related to time, they are called "time domain" displays.

·Choose the right sampling method
The timing analyzer is like a digital oscilloscope with 1-bit vertical resolution. Since it has only 1-bit resolution, it can only display two states - high or low. The timing analyzer only cares about the voltage threshold defined by the user. If the signal is above the threshold when sampled, it is displayed as high or 1, and the sampled signal below the threshold is displayed as low or 0. From these sampling points, a table consisting of 1 and 0 is obtained, which represents the 1-bit image of the input waveform. This table is saved in memory and can be used to reconstruct the 1-bit image of the input waveform, as shown in Figure 1.

Figure 1 Sampling points of a timing analyzer

Timing analyzers tend to square signals, which may seem to affect their usability, but if you need to observe several or even hundreds of signal lines at the same time to verify the timing relationship between the signals, then a timing analyzer is the right choice. Remember that each sample point uses a memory location. The higher the resolution (the faster the sample rate), the shorter the acquisition window.

· Transition Sampling
When we capture data on an input line with a data burst as shown in Figure 2, we must adjust the sampling rate to a high resolution (e.g. 4ns) to capture the fast pulse at the beginning. This means that a timing analyzer with 4K (4096 samples) memory will stop acquiring data after 16.4ms, preventing you from capturing the second data burst.

Figure 2 High-resolution sampling

In normal debugging work, we sample and save data without activity for a long time. They use the logic analyzer memory but cannot provide more information. If we know when the transition occurs, whether it is a positive transition or a negative transition, we can solve this problem. This information is the transition timing basis for effective use of memory.

To achieve transition timing, we can use a "transition detector" at the input of the timing analyzer and the counter. Now the timing analyzer only stores those samples before the transition, and the time interval between two transitions. With this method, only two memory locations are used for each transition, and no memory locations are occupied when the input does not change.

In our example, depending on how many pulses are present in each burst, the second, third, fourth, and fifth bursts can now be captured while maintaining a high timing resolution of up to 4ns (Figure 3).

Figure 3 Sampling using a transition detector

Glitch Capture
Glitch impulses are notorious for appearing randomly and causing catastrophic consequences. Timing analyzers can easily capture glitches by sampling the input data and keeping track of any transitions that occur between samples. In the analyzer, a glitch is defined as any transition that crosses the logic threshold more than once between two consecutive samples. To identify glitches, we need to "teach" the analyzer to keep track of all multiple abnormal transitions and display them as glitches.

Glitch display is a very useful function that can provide glitch triggering and display the data before the glitch, thus helping us to determine the cause of the glitch. This capability also allows the analyzer to capture only the data required when the glitch occurs.

Let's recall the example mentioned at the beginning of this section. We have a system that crashes periodically because a glitch appears on a signal line. Because the glitch occurs occasionally, even if you can save all the data over time (assuming there is enough storage capacity), it is difficult to find it in the huge amount of information. The alternative is to use an analyzer without a glitch trigger function. You have to sit in front of the instrument, press the run button, and wait until you see the glitch.

·Triggering of timing analyzer
The logic analyzer continuously captures data and stops the acquisition after finding the trace point. In this way, the logic analyzer can display the information before the trace point, which is called negative time, and the information after the trace point.

Pattern trigger

Setting the tracking characteristics of a timing analyzer is slightly different from setting the trigger level and slope of an oscilloscope. Many analyzers trigger on high and low patterns that span multiple input lines. To make things easier for some users, most analyzers allow trigger points to be set not only in binary (1s and 0s), but also in hexadecimal, octal, ASCII, or decimal. Using hexadecimal trigger points is more convenient when viewing buses that are 4, 8, 16, 24, or 32 bits wide. Imagine how much more troublesome it would be to set a 24-bit bus in binary.

Edge trigger

When you adjust the trigger level knob on an oscilloscope, you are setting a level on the voltage comparator that tells the oscilloscope to trigger when the input voltage crosses that level. Edge triggering on a timing analyzer is similar, but the trigger level is preset to the logic threshold. Most logic devices are level dependent, and the clock and control signals of these devices are usually edge sensitive. Edge triggering allows you to capture data synchronously with the device clock. You can tell the analyzer to capture data when a clock edge occurs (rising or falling) and get all the outputs of the shift register. Of course, in this case, the trace point must be delayed to account for the propagation delay through the shift register.

State Analyzer Basics

If you have never used a state analyzer, you might think it is an extremely complex instrument that takes a long time to master. In fact, many hardware designers find that there are many valuable tools in a state analyzer.

The "state" of a logic circuit is the sample of the bus or signal line when the data is valid. For example, take a simple "D" flip-flop. The data on the "D" input is not valid until the positive edge of the clock arrives. Thus, the state of the flip-flop is the state when the positive clock edge occurs.

Now, suppose we have 8 of these flip-flops connected in parallel. All 8 flip-flops are connected to the same clock signal. When a positive transition occurs on the clock line, all 8 flip-flops will capture data on their respective "D" inputs. Thus, a state is created every time a positive transition occurs on the clock line, and these 8 lines are similar to a microprocessor bus. If we connect a state analyzer to these 8 lines and tell it to collect data when the clock line transitions positively, the state analyzer will do so. Unless the clock transitions high, any activity on the input will not be captured by the state analyzer.

The timing analyzer is controlled by an internal clock to sample, so it samples the system under test asynchronously. The state analyzer gets the sampling clock from the system, so it samples the system synchronously. The state analyzer usually displays data in a list format, while the timing analyzer displays data in a waveform diagram.

Understanding the Clock

In a timing analyzer, sampling is done in the direction of a single internal clock, which makes things very simple. But in a microprocessor system there are often several "clocks". Suppose at a certain moment we want to trigger on a specific address in RAM and view the stored data; suppose the microprocessor used is a Zilog Z80.

To capture addresses from the Z80 with a state analyzer, we need to capture when the MREQ line is low. To capture data, we need to have the analyzer sample when the WR line is low (write cycle) or when the RD line is low (read cycle). Some microprocessors can multiplex data and addresses on the same line. The analyzer must be able to have the clock information come from the same signal line, rather than from a different clock line.

Figure 4 RAM Timing Waveforms

During a read or write cycle, the Z80 first places an address on the address bus. Next, the MREQ line is asserted to read or write the memory at that address. Finally, the RD or WR line is asserted depending on whether it is a read or write. The WR line is asserted only after the bus data is valid. In this way, the timing analyzer acts as a demultiplexer to capture the address at the appropriate time and then capture the resulting data on the same signal line.

Triggering State Analysis Like the timing analyzer, the state analyzer also provides the ability to limit the data to be saved. If we are looking for a specific pattern of high and low levels on the address bus, we can tell the analyzer to start saving when we find the pattern until the analyzer's memory is completely filled. This information can be displayed in hexadecimal or binary format. However, hexadecimal may be more convenient when decoding to assembly code. When using a processor, these specific hexadecimal characters should be compared with the processor instructions. Most analyzer manufacturers have designed software packages called disassemblers that translate the hexadecimal code into easy-to-read assembly code.

Figure 5 Translating hexadecimal code into assembly code

Sequence level and selective storage

State analyzers have "sequence level" data that helps trigger and store. Sequence level allows you to define the data to be stored more precisely than a single trigger point. This means that a more precise data window can be used without storing unnecessary information.

Selective storage means that only a portion of a larger whole can be stored. For example, suppose we have an assembly routine that calculates the square of a given number. If the routine does not calculate the square correctly, we tell the state analyzer to capture the routine. Specifically, we tell the state analyzer to find the beginning of the routine. When it finds the starting address, we tell it to find the ending address and save all information between the two. When it finds the end of the routine, we tell the analyzer to stop state storage.
Probing Solutions For debugging, the physical connection applied to the digital system must be convenient and reliable, with minimal intrusion to the target system being debugged, so that the logic analyzer can get accurate data. A common probing solution is a passive probe with 16 channels per cable. Each channel is terminated at both ends with 100kΩ in parallel with 8pF. You can compare the electrical performance of this passive probe to that of an oscilloscope probe. In addition to being smaller and more reliable, a passive probing system allows the probe to terminate at the point of connection to the target system. This avoids the added stray capacitance from the large active probe interface clip to the large number of leads between the circuit under test. As a result, your circuit under test only "sees" 8pF of load capacitance instead of the 16pF of the previous probing system.

Figure 6 Analysis probe

Connecting a state analyzer to a microprocessor system requires mechanical connections and clock selection. Some microprocessors may require external circuitry to decode some signals to derive the clock for the state analyzer. Analysis probes not only provide a fast, reliable, and correct mechanical connection to the target system, but also provide the necessary electrical adaptation capabilities, such as clocks and demultiplexers, to properly capture the system operation.

Conclusion

Most logic analyzers consist of two main parts: a timing analyzer and a state analyzer. The timing analyzer is more suitable for handling multi-line bus structures or applications. It can trigger on the pattern on the signal line, or even on glitches. The state analyzer is often seen as a software tool, but it is also useful in hardware settings. Since it gets the clock from the system under test, the data captured is the data of the system on the clock. Logic analyzers provide powerful design tools for digital circuit designers.