Audio and video SoC test requirements and applications

As SoCs and SIPs in high-volume consumer industries become more complex, the conflict between the two basic requirements of low cost and high device life cycle becomes more prominent. Consumers demand improved performance at the same or lower cost, and often propose new improvements. Therefore, components must be thoroughly tested at low cost and extremely quickly.

While greatly reducing the throughput overhead of the ATE architecture, it can provide more parallel processing capabilities in testing, which may properly solve the additional time problem caused by testing increasingly complex devices. In order to solve the emerging analog core problems in cutting-edge consumer devices, in addition to the above two measures, the resolution and accuracy of ATE hardware must be guaranteed.

Audio DAC and ADC

highly integrated SoC devices, such as the wireless mobile phone baseband processor shown in Figure 1, have multiple functional blocks with different performance built in, and are under the dual pressure of specifications and test time.

Simple 10-bit effective resolution and 4KHz bandwidth met the audio quality requirements of early wireless handsets. Recent developments indicate that devices can support CD-quality audio performance with more stringent specifications, stereo and surround sound effects. The market claims 24-bit audio resolution, but the actual effective performance is generally 16-bit to 17-bit, equivalent to 98dB to 104dB dynamic range and 20KHz bandwidth.

When discrete CD-quality DACs and ADCs were used in the consumer market, the ATE-related test costs were manageable due to the initiative to increase device prices. When CD-quality cores are integrated into SoCs, the increase in device prices can no longer offset the increase in ATE test costs due to the increased test time and negative impact on the cost of test (COT) caused by the additional functions.

Audio Core Test Time Derivation Example

For mixed signal dynamic testing, it is critical to prevent spectrum leakage in the spectrum generated during the analysis process. Therefore, the following relationship must be satisfied:

M/N=Ft/Fs

Where M is the number of capture cycles; N is the number of sampling points; Ft is the test signal frequency; Fs is the sampling frequency.

For low-fidelity audio devices, such as microphones with ADC inputs or headphones with DAC outputs, an 8KHz sampling rate is used, which is equivalent to a 4KHz bandwidth. If the test signal frequency is 1.03125KHz, 66 cycles can be captured relative to an 8KHz sampling rate and 512 points. The sampling time is equal to the number of sampling points divided by the sampling frequency, which is 64ms. Audio testing requires more than 10 tests, including multiple gain states; idle channel noise (ICN), crosstalk (XTALK) and intermodulation distortion (IMD). This means that even for a simple core, the total test time is 650ms.

The test overhead of transferring 20-bit sampled data from the ATE's analog or digital capture memory to the workstation is also considerable. To determine the amount of data to be transferred for analysis, multiply 20 bits by the number of sampling points N, and then multiply it by the number of measurements of the test core. In this example, 20 bits × 512 points × 10 measurements total 102400 bits. Assuming a 1MB bandwidth between the analog module and the workstation, the transfer time to test the DAC core is approximately 100ms. The digital capture memory transfer overhead is also 100ms at the same bandwidth. Therefore, for voice quality DAC and ADC testing, the 200ms transfer overhead increases the total test time to 1500ms (650ms + 650ms + 200ms).

Parallel Test Overhead of ATE Architecture

To further illustrate this issue, consider the impact of a surround sound audio processor on test time. AC3 digital audio provides 6 analog outputs: front L/R; surround L/R; center speaker and subwoofer. From an analog point of view, these devices require a combination of high dynamic range and parallel test.

CD quality dynamic range and bandwidth require a higher sampling rate. Using the above formula and substituting Fs = 4.8KHz, the sampling time is 10.7ms. Taking into account hardware setup, test stabilization and other overheads, the test time is 15ms. Taking into account the number of measurements of more than 10 times, the total test time rises to 150ms. Thus, for each position with 6 channels, the serial test implementation will take 900ms.

The 4-test point implementation can take full advantage of the parallel testing of multiple waveform digitizers. However, data transmission is still serial in multi-test point testing, and the transmission overhead is cumulative. Therefore, even with 4 waveform digitizers, the 4-test point test implementation takes 900ms + 4 × 600ms = 3300ms.

Multi-standard wireless baseband processors

Wireless devices set multiple standards in the same mobile phone. To support these standards, chipsets often have redundant baseband analog converters and RF transceivers. For example, in audio surround sound processors, the numerous analog cores in wireless baseband processors have a huge impact on test time. The main challenge in testing these devices is how to set up sufficient parallel testing in the analog test hardware to obtain the efficiency of multiple test points.

The baseband processor block consists of orthogonal (I/O) transmit (TX) DAC and receive (RX) ADC pairs. In 2G to 2.75G GSM/GPRS/EDGE technology, the carrier channel spacing is limited to 200KHz, resulting in low-frequency zero IF. W-CDMA uses 5MHz channels, which corresponds to a wider bandwidth.

Full dynamic testing is usually required for the RX and TX paths, including signal pair distortion (SND), CIN, and XTALK. I/Q pairs DACs and ADCs also require gain matching and phase matching tests, with specifications specified within 0.1dB and 3 degrees of high accuracy, respectively. The requirement to ensure channel isolation during transmission leads to additional out-of-band (OOB) attenuation testing of the DAC. Adjacent channel power ratio (ACPR) can confirm the degree of channel isolation, and for W-CDMA DACs, the OOB frequency can be verified up to 10MHz.

High-definition video encoders

Current SoC devices support a variety of video input standards. Traditional NTSC or PAL devices are equipped with super video CS-VIDEO and composite analog outputs. Supporting HDTV requires 3 additional outputs to provide signals that comply with YPrPbHDTV (EIA-770.1-3). 6 video DACs are required to prepare all the above outputs: 2 for S-Video, 1 for composite output, and 3 for RGB.

Although the digital video standard requires a maximum interface speed of 74MHz, the analog bandwidth required to test DAC performance is about 8MHz and the resolution is 10 to 12 bits. Typical test items for a single video DAC include integral nonlinearity (INL), differential nonlinearity (DNL), and SND measurements. The picture quality of the HDTV system is determined by the relative accuracy of the DAC output, and additional tests must be performed on the output gain and phase matching. The total test time of the built-in digital video device is directly related to the number of parallel digitizers available for testing. The number of video DACs to be tested is usually more than 6, and due to the lack of tester resources, it is essential to establish a serialized test solution.