Static RAM structure diagram

Figure 2.2 (1) Schematic diagram of static RAM structure

The structural composition diagram of the static RAM is shown in Figure 2.2 (1). The storage body is a storage matrix composed of 64×64=4096 six-tube static storage circuits. In the storage matrix, the output end of the X address decoder provides 64 row selection lines, X0 to X63, and each row selection line is connected to the row selection end of the 64 storage circuits in the same row, so the row selection line can simultaneously provide row selection signals for the 64 row selection ends of the row. The output end of the Y address decoder provides 64 column selection lines, Y0 to Y63, and the 64 storage circuits in the same column share the same bit line, so the column selection line can simultaneously control them to connect with the input/output circuit (I/O circuit). Obviously, only when a unit storage circuit with both rows and columns selected is opened at the same time, can the operation of reading and writing information be performed.

The memory shown in the figure is a memory with a capacity of 4K×1 bit, so it has only one I/O circuit. If a memory with a word length of 4 or 8 bits is to be formed, then each time it is accessed, 4 or 8 unit storage circuits should exchange information with the outside world at the same time. In this memory, the columns are grouped by 4 or 8 bits, and each column select line controls a group of column gates to open at the same time; accordingly, there should be 4 or 8 I/O circuits. The same bit in each group shares an I/O circuit. Usually, the storage capacity of a RAM chip is limited, and several chips are needed to form a practical memory. In this way, storage units with different addresses may be in different chips. Therefore, when selecting an address, the chip to which it belongs should be selected first. For each chip, there is a chip select control terminal ( ), and only when a valid signal is added to the chip select terminal can the chip be read or written. Generally, the chip select signal is generated by decoding the high bit of the address code.