20-bit monolithic audio digital-to-analog converter PCM63P

　　PCM63P is an ultra-low distortion 20-bit precision DAC chip produced by BB using a unique dual DAC collinear structure. This structure can eliminate harmful digital-to-analog induced interference errors and other nonlinearities near the bipolar zero point. Therefore, the noise of the PCM63P is very low. The maximum SNR is 116dB. It also has 16 times oversampling rate and fast settling time current output. 200ns at 2mA step. The following are the main features of PCM63P:

　　●It is a collinear 20-bit audio DAC;

　　●Can work at low level almost ideally;

　　●Output countless modes of induction interference;

　　●Can quickly (200ns) current output (±2ms);

　　●With industry standard serial input interface;

　　●Ultra-low distortion, maximum -96dB (no external adjustment);

　　●With reference source;

　　●The minimum SNR is 116dB (calculated based on weighted method);

　　●Has 16 times oversampling capability.

　　2 Structural function

　　Figure 1 shows the internal structural block diagram of the PCM63P digital-to-analog conversion chip. Figure 2 shows its pin arrangement, and the function of each pin is as follows:

　　CAP (pin 1): Servo amplifier decoupling capacitor access terminal;

　　+VA (pin 2): +5V analog power supply;

　　CAP (pin 3): reference decoupling capacitor access terminal;

　　CAP (pin 4): offset decoupling capacitor end;

　　BPO (pin 5): bipolar bias current output port, typical bias current output is +2mA;

　　IOUT (pin 6): DAC current output;

　　ACOM (pin 7): Analog common terminal;

　　RF1 (pin 9): Feedback access terminal;

　　RF2 (pin 10): There is a 1.5kΩ feedback resistor inside the chip between this pin and pin 9 for external feedback;

　　-VD (pin 11): -5V digital power supply;

　　DCOM (pin 12): digital common terminal;

　　+VD (pin 13): +5V digital power supply;

　　CLK (pin 18): DAC data clock input;

　　LE (pin 20): DAC data latch allowed;

　　DATA (pin 21): DAC data output;

　　UB2 Adj (pin 23): Select high DAC bit 2 adjustment (-4.29V);

　　LB2 Adj (pin 24): Select low DAC bit 2 adjustment (-4.29V);

　　VPOT (pin 25): Bit adjustment reference voltage tap (-3.25V);

　　-VA (pin 28): -5V analog power supply;

　　NC (other): empty foot.

　　3 Working principle

　　3.1 Dual DAC collinear structure

　　PCM63P adopts a new design. It combines the advantages of traditional DACs (good full-scale performance, high signal-to-noise ratio and ease of use) with excellent low-level performance. The two DACs inside it are combined in a complementary manner to produce good linear output. The two DACs share a reference source and R-2R ladder network, ensuring complete tracking under all conditions. They achieve high-precision matching between DACs by swapping individual bits of the DAC with laser-calibrated precision resistors.

　　This new complementary linear structure adopted by PCM63P is also called dual DAC collinear structure. This structure can leave the zero point with small steps in both directions, thereby avoiding any misoperation or "large" linear error, and at the same time it can Provides an absolute current output. The PCM63P's low-level performance ensures its 20-bit accuracy, especially near critical bipolar zeros.

　　3.2 Dynamic indicators

　　An important dynamic indicator of PCM63P is total harmonic distortion + noise (THD + N). PCM63P reads digital data at 8 times the standard audio sampling frequency of 44.1kHz, thereby achieving 991Hz sine wave output. . The dynamic range of its audio conversion can be seen as a measurement of THD+N at an effective output signal level of -60dB relative to 0dB. At the -90dB output level, the PCM63P's deviation from the ideal signal is generally less than ±0.3dB. These performances reflect the near-ideal performance of the PCM63P collinear DAC circuit at low noise and near bipolar zero.

　　4 Applications of PCM63P

　　4.1 Digital input

　　The PCM63P is capable of receiving TTL-compatible logic levels. On the input line, the logic input structure using differential current mode improves the anti-noise interference capability of the PCM63P. The data format of PCM63P adopts two's complement format, which is a serial data stream with the most significant bit first. Any number in the bit string can be loaded before 20 bits of data, because after LE (register enable signal) goes low, only the last 20 bits of data before it can be transferred to the parallel DAC register.

　　In the PCM63P chip, the serial data input bits of the DAC are triggered on the rising edge of the clock CLK, and the conversion of the DAC's serial to parallel data is performed on the falling edge of the enable signal LE. The conversion timing diagram is shown in Figure 3. The typical clock rate of PCM63P is 16.9MHz.

　　4.1 Power supply and filter capacitor

　　The PCM63P application circuit connection diagram using internal feedback resistor is shown in Figure 4, which adopts voltage output mode. If no feedback resistor is used, pins 9 and 10 of PCM63P should be left floating. PCM63P uses a ±5V power supply. The two positive power supplies should be connected to the same point, as should the negative power supply. At the same time, decoupling capacitors should be added to each power supply pin to maximize power supply interference suppression. Both common points should be connected to the analog planes and should be as close to the chip as possible.

　　In fact, the circuit in Figure 4 has no special requirements for the decoupling capacitor, and the size requirements for the bias decoupling capacitor are not strict, but using a larger value capacitor will have better SNR performance. Additionally, all capacitors in the circuit should be as close as possible to the chip pins to reduce noise induced from surrounding circuitry.