Design of remote ECG medical signal monitoring system

1 Introduction

HHCE (Home Health Care Engineering) is gradually entering people's lives as people pay more attention to health and telemedicine develops. It advocates the concept of "seeking medical treatment at home, self-care, and remote diagnosis", combining high technology with medical treatment. The emergence of HHCE is in line with the trend of aging society, rising medical expenses, and high quality of life and health in the 21st century. At the same time, it can realize the sharing of medical resources and improve the medical level in remote areas, so it has a particularly strong vitality.

The HHCE system provides an effective and convenient medical monitoring solution for families, community medical care, and visiting doctors. The monitor with ECG signal monitoring function is an important part of the HHCE system. Domestically, the research on this type of product is just in its infancy, and the remote network simply completes the storage and transmission of database medical data, and has not yet truly completed the combination of network and medical equipment. Internationally, countries around the world have invested a lot of money in research in this area, but they still mainly use expensive instruments to complete medical data collection, and then rely on PC/internet networks to complete data collection and network diagnosis.

This design uses Altera's NiosⅡ soft-core processor as the CPU, and transplants the current mainstream μClinux operating system. The system has the characteristics of system stability, portability, function upgradeability, user-oriented, and remote control. On the one hand, it combines home health care and telemedicine, and is mainly designed for user terminals, so that individuals can easily self-detect and analyze their own ECG signals and understand their physical health status in real time; on the other hand, the collected data can also be stored through a memory card for long-term analysis and diagnosis of the data; in addition, the system can also quickly establish a connection with the medical care service end (such as hospitals, private doctors, monitoring centers, health centers, etc.) through remote communication facilities such as the Internet, and transmit the measurement data to a remote database or doctor. It is conducive to database management of medical information and remote real-time monitoring and diagnosis, so that users can get the most timely and effective diagnosis without leaving home.

2 System Introduction

The remote ECG medical signal monitoring system is mainly composed of four key modules: the front-end acquisition and conditioning module of ECG signal, the ECG signal processing and storage module, the data display module and the remote transmission control module. The system functional structure is shown in Figure 1.

The hardware platform of this monitoring system adopts Altera's CycloneⅡ2C35 FPGA chip, and adopts SOPC (system on a programmable chip) technology to integrate NiosⅡ soft-core processor, memory, functional interface and expansion I/O port on a FPGA chip. The peripheral expansion hardware such as ECG data acquisition board, network, LCD screen, touch screen/keyboard, SD memory card, etc. realize the hardware architecture of the system, and it has expandable I/O interface to facilitate the future upgrade and expansion of system functions.

3 Design of key system modules

3.1 Introduction to NiosⅡ Embedded Soft-Core Processor

The NiosⅡ series embedded processors are soft-core processors launched by Altera. Users can get more than 200 DMIPS performance with less than 35 cents of FPGA logic resources. NiosⅡ supports a variety of real-time operating systems such as MicroC/OS-Ⅱ and μClinux, supports lightweight TCP/IP protocol stack, allows users to add custom instructions and custom hardware acceleration units, seamlessly transplant custom peripherals and interface logic, and facilitates user design while improving performance.

The NiosⅡ processor uses the Avalon switching bus, which is a dedicated internal connection technology developed by Altera. The Avalon switching bus is automatically generated by SOPC Builder and is an inline bus used between system processors, internal modules, and peripherals. The Avalon switching bus uses minimal logic resources to support data bus multiplexing, address decoding, wait cycle generation, peripheral address alignment, interrupt priority specification, and advanced switching bus transmission.

3.2 ECG signal acquisition and conditioning module design

The ECG signal acquisition adopts a modular design, which is mainly composed of the front-end lead sensor, signal filtering, amplification and conditioning circuit and A/D sampling circuit. The main frequency range of human ECG signals is 0.05-100 Hz, the amplitude is about 0-4 mV, and the signal is very weak. At the same time, ECG signals are usually mixed with other bioelectric signals, and the electromagnetic field interference mainly based on 50 Hz power frequency interference in the body makes the ECG noise background strong and the measurement conditions are relatively complicated. In order to detect ECG signals with clinical value without distortion, the signal filtering and amplification conditioning part is mainly composed of the following circuits: preamplifier circuit, high and low pass filter circuit, notch circuit and A/D conversion circuit. The circuit schematic is shown in Figure 2.

First, the weak ECG signal collected by the ECG lead is amplified by the preamplifier circuit, which includes the right leg drive to suppress common-mode interference and the shielded line drive to eliminate lead interference. The gain is set to about 10 times. The preamplifier is designed to use the medical amplifier AD620 produced by Analog Devices of the United States. AD620 is developed from the traditional three operational amplifiers and is an integration of in-phase parallel differential amplifiers. It has the characteristics of wide power supply range (±2.3～±18 V), small design volume, and low power consumption (maximum power supply current is only 1.3 mA), so it is suitable for low-voltage and low-power applications. In addition, it also has the advantages of high common-mode rejection ratio, good temperature stability, wide amplification bandwidth, and low noise coefficient. The amplified signal is filtered and 50 Hz notch processed before secondary amplification, and the gain of the latter stage is set to about 100 times. Since the maximum amplitude of the ECG signal is only a few mV, and the amplitude of the input signal in the A/D conversion is required to be above 1 V, the total gain is set to about 1 000 times. The filtering adopts the voltage-controlled voltage source second-order high (low) pass filter circuit to eliminate the interference signals such as electromyography outside the 0.05-100 Hz frequency band, and the other high-order harmonics in the power frequency can also be filtered out. At the same time, the active double-T band-stop filter circuit is used to further suppress the 50 Hz power frequency interference.

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The A/D sampling chip uses TI's 8-bit serial chip TLC549, which uses an SPI interface and can achieve acquisition control and data transmission with only three lines; it has a 4 MHz on-chip system clock and software and hardware control circuits, a conversion time of less than 17μs, and a sampling rate of 40kS/s; using the differential reference voltage technology, the minimum value that TLC549 can measure is 1 000 mV/256, which means that 0-1 V signals can obtain 8-bit resolution without amplification.

3.3 Data Acquisition Controller Design

In order to obtain the ECG signal converted by the front-end TLC549 chip, a data acquisition controller must be designed to control the AD chip and obtain digital ECG data. The controller is designed by VerilogHDL according to the working timing of the TLC549 chip and the needs of back-end data processing. The controller has the characteristics of multi-channel acquisition.

During the period of inputting 8 external clock signals from the I/O CLOCK terminal of TLC549, the following tasks need to be completed: read in the previous A/D conversion result; sample and hold the input analog signal of this conversion; start this A/D conversion. Then the acquisition time of one channel is: 0.5μs×(3+8×2+1)=10μs, and the chip conversion time is less than 17μs, so the whole process takes 27μs. In order to effectively utilize the controller, during the A/D conversion of one channel, another A/D sampling is performed at the same time, so that the acquisition of four channels of signals can be completed within 40μs, which greatly improves the work efficiency. At the same time, a FSM signal is added to the design to control the sampling time, so as to adapt to the sampling frequency of signals with different frequencies. The timing simulation diagram of the AD chip is shown in Figure 3.

Din is the serial input of the collected data, and the clock is obtained by the system clock through the frequency division coefficient. In the design, fsm is set as the sampling control clock, so that the sampling rate can be adjusted as needed. Since the time for an AD sampling is very short, it is unrealistic to use query or interrupt to read directly. This requires the use of buffer design to reduce the number of interrupts by temporarily storing the data converted N times in the buffer memory. In order to obtain continuous and correct collected data and achieve seamless buffering, this design adopts a ping-pong operation structure of double buffer storage in view of the flexibility of FPGA design. This design implements data caching by alternately storing the AD sampling timing controller in two 512 B dual-port RAMs (DPRAMs). When one of the DPRAM1 is full, it is transferred to the other DPRAM2 and an interrupt is generated. In this way, when the controller writes data to DPRAM2, the system will have sufficient time to retrieve the data in DPRAM1.

3.4 Display module design

In order to be able to intuitively display the collected ECG waveform, the support of the display device is required. The LCD panel used in this design is a TFT 320*240 LCD. The LCD module does not have a display controller, so it is necessary to design a display controller IP core to drive the LCD panel. The display controller IP core implemented in this design is designed using Verilog HDL and supports multiple color modes, including 18bpp, 16bpp, 8bpp and custom modes. The image memory lcd_fifo uses an on-chip FIFO, which can be word-sorted as needed. The 256-color color lookup table is stored in the on-chip RAM. Image information can be transmitted through the burst block transfer method written to the AvaIon bus master port, and automatically read from the memory using DMA. A dedicated DMA channel is established between the SDRAM image memory image_ram and the on-chip image data buffer lcd_fifo. The controller structure is shown in Figure 4.

The LCD controller IP core is mainly composed of four modules: interface module, memory module, color conversion module and timing module.

The interface module mainly uses NiosⅡ processor to control LCD controller and read the status. The interface module mainly exists in the form of registers, including control register, status register, DMA address register and interrupt register.

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The memory module is the main interface part of the Avalon bus. After the system is started, the DMA transfer mode is used to complete the independent reading of the image data in the image data memory image_ram to the on-chip image data buffer lcd_fifo through the burst block transfer method written by the Avalon bus master port. The DMA transfer method is used to free the NiosⅡ soft-core processor from the frequent data reading operation, which can greatly improve the system's work efficiency.

The color conversion module converts the read data according to the four color modes. The 8bpp and custom modes need to be connected to the color lookup table due to insufficient colors. The custom mode can manually preset the address of the palette to define the output color.

The timing module is written strictly according to the timing of LCD, where the LCD clock is 5 MHz. The lcd_fifo data output is started by controlling the data enable signal, and the display is scanned line by line. At the same time, when designing this module, before the data valid signal (DE) is valid, it is necessary to check whether there is data in the lcd_fifo to determine whether to read and transmit the data; the palette mode must be set, and the mode needs to be locked during the frame transmission process to avoid transmission errors; different reading time periods must be determined according to different bpp modes, 18bpp is read every time, 16bpp is read once at intervals, and 8bpp is read four times at intervals.

3.5 Data Storage Module Design

This design uses SD card as an external storage hard disk. SD memory card is a multifunctional memory card with large capacity, high performance and good security. It is widely used in portable devices such as digital cameras, PDAs and mobile phones. All units on the SD card are clocked by the internal clock generator, and the interface driver unit synchronizes the DAT and CMD signals of the external clock to the internal clock. There are two communication protocols for SD cards, namely SD communication protocol and SPI communication protocol. Compared with the SPI communication protocol, the biggest advantage of the SD communication protocol is the fast reading and writing speed. Theoretically, a single data line can reach 25 MB/s, and four-line transmission can reach 100 MB/s. This design uses the four-line SD communication protocol.

In this design, the SD card protocol is written by software: First, six I/O ports are defined in SoPC Builder: SD_CMD, SD_DAT0-DAT3, SD_CLK, which correspond to the command, data, and clock ports of the SD card respectively. Then, a C program is written on NiosⅡIDE according to the SD card transmission protocol to operate the six I/O ports, so as to implement the SD card transmission protocol. The file system is transplanted on the basis of completing the reading and writing of the SD card data block. FAT16, in this way, saves FPGA resources without affecting the reading and writing speed.

3.6 Data transmission module design

In order to achieve remote data exchange, this system uses Ethernet for data transmission. The design uses DM9000A as the Ethernet control chip. DM9000A is a high-speed network controller from DAVICOM, with a general processor interface, a 10/100M PHY and 4kB SRAM. In order to achieve network data transmission, the design needs to complete the following tasks: porting the μClinux operating system on NiosⅡ, completing the design of the network bottom driver, and developing applications based on the network protocol. Among them, the work of porting the μClinux operating system on NiosⅡ has been completed, so the key task of this design is to complete the network driver design and application development.

The design of HAL device driver based on DM9000A is mainly divided into two steps: first, the Avalon bus interface logic design of DM9000A; second, the read and write driver design of DM9000A; finally, the driver of DM9000A is transplanted into HAL according to the driving mode of HAL. DM9000A communicates with NiosⅡ as a slave peripheral of Avalon bus. The Avalon bus interface logic of DM9000A mainly completes the connection between chip signal and Avalon bus interface signal.

DM9000A does not allow direct access to the registers inside the chip, and requires reading and writing through the data port and index port. These two ports are controlled by the CMD pin: when CMD is connected to a high level, it is a data port, and when CMD is connected to a low level, it is a control port.

Creating a HAL device driver includes: creating a device instance and registering the device. In the design, for the LWIP structure, define a structure as the alt_dev structure of the DM9000A device:

When NiosⅡ starts, the device will be initialized in aIt_sys_init(). The initialization procedure is as follows:

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The application program is designed using TCP/IP and HTTP protocols, with the monitor as the Web server and the remote PC as the client to display the collected ECG waveforms through the web page.

4 Experimental Results

The system collects human ECG signals and displays them in real time on an LCD panel. The data is stored on an SD card and sent to a remote PC via an Ethernet network. The following are the verification and test results of the system functions.

4.1 Signal Acquisition and Conditioning Module

The ECG signal acquisition and conditioning module is a self-designed acquisition board, and the main measurement parameters are the channel bandwidth, amplification capability and notch characteristics of the preamplifier. After testing, the test signal amplification gain is basically stable at 12.1 dB in the frequency bandwidth of 1 to 1 kHz, that is, its channel bandwidth can be ≥1 kHz; when the frequency is 20 Hz and 50 Hz, the amplifier's amplification capability gain for 40 to 800 mV signals does not change significantly, and is basically stable at 11.7 to 13.1 dB; at the same time, the notch filter can control the amplification gain to less than 0.5 dB when filtering the 50 Hz signal. Therefore, the acquisition and conditioning module designed based on the characteristics of the ECG signal can stably obtain the ECG signal of the human body.

4.2 Signal display module

Figure 5 shows the real-time display of the collected ECG signal through the local LCD panel. From the display results, the five characteristic points of the ECG signal, PQRST, are obvious, the waveform is smooth, and it is stable and interference-free in actual measurement, which can truly reflect the collected ECG signal.

4.3 Network transmission module

In the design, the realization of the network interface function enables the collected ECG signals to be sent to the remote PC via Ethernet, realizing remote data transmission. According to the TCP/IP protocol and HTTP protocol, the signal is sent to the network after being packaged. On the remote PC, the ECG waveform collected by the server can be viewed through a web browser. Figure 6 shows the display result of the ECG signal on the web browser of the remote PC. The test result shows that it is basically consistent with the waveform displayed on the local LCD panel, realizing the remote transmission function.

Experiments show that the ECG monitoring system can realize data collection, display, storage and transmission functions in real time and accurately.

5 Conclusion

This paper describes the design of a remote ECG medical signal monitoring system based on the NiosⅡ soft-core processor. The design has completed the construction of the system platform and passed the EDA software simulation verification and board-level verification on the DE2 development board. It can realize the acquisition and conditioning of ECG signals, LCD display of signal waveforms and data, data storage, and network transmission.

The design uses SOPC technology and IP core reuse technology to shorten the system development cycle, while making the system portable, flexible, and functionally expandable. By transplanting the μClinux operating system, the system has powerful network functions and stronger system stability.