Data Transmission Bus Converter Based on FPGA+DSP+ARM

When testing flight control components, since the system under test is at a certain distance from the host computer, if the telemetry parallel data is directly transmitted to the host computer, data signal attenuation and signal delay problems will occur, which may cause signal timing misalignment and thus fail to meet the system test requirements. For this reason, it is necessary to develop a data transmission bus converter to complete the undistorted, real-time, long-distance communication between the tested data and the host computer, and to receive control commands from the host computer to achieve remote interaction of the working status.

1 Overall design of data transmission bus converter

Taking into account the real-time and reliability requirements of the test system, the Ethernet port is selected as the data forwarding interface between the data transmission bus converter and the host computer, the high-speed serial port is used as the control port, and the FPGA+DSP+ARM architecture is used as the real-time information processing platform.

The system block diagram of the data transmission bus converter is shown in Figure 1. Among them, FPGA, as a data preprocessor, completes data preprocessing tasks such as conversion from parallel data to serial data; DSP reads the data processed by FPGA and completes the task of data compression; ARM, as a central processing controller, mainly completes the task of reading the encoded data from the DSP system and completing the real-time communication task with the host computer through the Ethernet port. The host computer demodulates various physical variables according to the data transmission protocol and the product's data telemetry protocol, records and stores them. The tester completes the remote control of the working status and various information interaction tasks through the host computer.

The high-end architecture of FPGA+DSP+ARM is adopted in this system. However, the overall performance of a system should not only be measured by the devices used and the functions completed, but also by the interface form between the devices. On the information processing platform of FPGA+DSP+ARM, the interface form between the three will determine the performance of the entire system. In order to meet the real-time signal processing tasks, when selecting a DSP chip, not only the processing speed of the DSP chip should be considered, but also the interface capability of the DSP chip with FPGA and ARM. Selecting a DSP with EMIF and HPI interfaces to seamlessly connect it with FPGA and ARM has become a key link in the design of this system.

2 Device Selection

In this data transmission bus converter, the FPGA uses the XC3S500E from the Spartan-3E series, the latest low-cost field programmable gate array launched by Xilinx. The XC3S500E contains 20 Block RAMs, and each RAM block has 18 KB of module memory, which is a fully synchronous, true dual-end memory. Users can read from or write to each port independently (but the same address cannot be read and written at the same time). In addition, each port has an independent clock, and the data width of each port can be configured independently.

The ARM chip used is Samsung's S3C4510B. The S3C4510B is a cost-effective 16/32 bit RISC microcontroller based on Ethernet application systems, which contains a 16/32 bit ARM7TDMI RISC processor core designed by ARM. In addition to the ARM7TDMI core, the S3C4510B also has many important on-chip peripheral function modules, including an Ethernet controller for network communication between the S3C4510B system and other devices.

The DSP chip used is TMS320C6416 from TI. TMS320C6416 is a high-speed fixed-point DSP launched by TI. It has a powerful CPU, up to 1 MB of RAM, and rich peripheral interfaces. The peripherals include flexible external memory interfaces EMIFA and EMIFB that provide seamless interfaces for CPU access to peripheral devices, a PCI interface that makes it easy for the DSP to seamlessly connect to an external main CPU with PCI functions through the PCI interface, a 16/32 bit wide asynchronous parallel interface HPI (sharing the same pins as PCI), and an enhanced EDMA that provides 64 bit data channel access. Its high processing speed meets the real-time requirements of the system and can achieve seamless connection with a variety of peripherals. [page]

3 Hardware Design

3.1 Interface circuit between ARM and DSP

3.1.1 DSP TMS320C6416 HPI Description

TMS320C6416 integrates a 16/32 bit wide host interface HPI. HPI selects whether to use HPI16 or HPI32 through the bootstrap at reset and the device configuration pin HD5. HPI has two address lines HCNTRL[1:0], which are responsible for addressing the internal registers of HPI. HPI has only three 32 bit internal registers, namely the control register HPIC, the address register HPIA and the data register HPID. Users only need to perform corresponding read and write operations on the above three registers to complete the access to the DSP memory space.

3.1.2 Interface circuit between S3C4510B and TMS320C6416

Since there is no external interface in S3C4510B that fully complies with the TMS320C6416 HPI interface timing that can be used directly, the external I/O interface in S3C4510B with the timing closest to the HPI interface timing is selected to be connected to TMS320-

C6416. The interface circuit between TMS320C6416 and S3C4510B is shown in Figure 2. TMS320C6416 and S3C4510B are connected through separate 32-bit data lines HD0~HD31 and 8 control lines. S3C4510B accesses the RAM inside the DSP and other external resources through the HPI interface. In the entire process of communication and data exchange between the ARM microprocessor and the DSP chip through the HPI interface, except for interrupting ARM and clearing the interrupt sent by ARM, which requires the participation of DSP itself, the DSP is in a passive position in other operations and almost no other operations are required. Therefore, for ARM, the DSP system unit is equivalent to an external SDRAM.

In TMS320C6416, HPI, GP[15:9], PCI, EEPROM, and McBSP2 share a set of pins. When the DSP is reset, it selects which peripheral to use by latching the values ​​of the PCI_EN and McBSP2_EN pins. In this system, both enable pins are pulled low.

3.2 Interface circuit between FPGA and DSP

3.2.1 DSP TMS320C6416 EMIF Description

TMS320C6416 has two external EMIF bus interfaces, namely 64-bit EMIFA and 16-bit EMIFB. The EMIFA interface has the function of interfacing with 8, 16, 32, and 64-bit systems, and the EMIFB interface port supports 8-bit and 16-bit systems. EMIFA is a 64-bit memory bus, divided into 4 storage spaces ACE0~ACE3, each of which can be configured independently, and the seamless interface has multiple types of memory, such as SRAM, Flash RAM, and DDR RAM.

3.2.2 Interface circuit between FPGA and TMS320C6416

In this system, the DSP TMS320C6416 EMIFA interface is used to connect to the FPGA to achieve seamless connection between the DSP and the FPGA Block RAM. One end of the FPGA's dual-end Block RAM communicates with the DSP in memory mode, and the other end communicates with the internal FPGA logic.

Since EMIF has flexible timing parameters and requires very little FPGA logic, FPGA can be used as a DSP coprocessor with minimal design effort. Figure 3 shows the interface circuit between TMS320C6416 and FPGA.

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4.1 Embedded Operating System

In the data transmission bus converter, the task of real-time data compression is completed by DSP. ARM S3C4510B completes the Ethernet communication between PC and the real-time, reliability and complexity required by its software implementation make it necessary to choose an embedded real-time operating system with TCP/IP protocol package. μCLinux is an operating system with a complete TCP/IP protocol. The real-time RT-Linux module is added to μCLinux to meet the real-time requirements of the embedded operating system.

4.2 Driver and Application Development

The development of hardware drivers and applications based on the μCLinux operating system is carried out in a cross-compilation environment. First, they are developed on a PC, then ported to a target machine for debugging and finally fixed to the target machine. The hardware drivers developed include Ethernet card controller drivers, LCD drivers, HPI drivers, and other drivers. The system software structure is shown in Figure 4.

Three tasks are run on the μClinux operating system: reading compressed data, sending data via Ethernet, and receiving and executing commands from a remote PC. The task of reading DSP compressed data requires real-time performance and is implemented through an interrupt handler, while the other two tasks are implemented through user processes. The task of sending data via Ethernet and the task of reading compressed data share a buffer, and the address of the buffer bidirectional linked list is passed between them through the ioctl function. Therefore, a driver needs to be registered for the communication interface HPI on the data processing module. The function to register the driver is:

result=register_chrdev(HPI_MAJOR,"hpi",&hpi_fops)

The main structure of the driver is as follows:

struct file_operations hpi_fops=

{

owner: THIS MODULE,

open: hpi_open,

read: hpi_read,

write: hpi_write,

ioctl: hpi_ioctl,

mmap:hpi_mmap,

release:hpi_release,

};

After the HPI driver is written, put the driver source code in the ../linux-2.4.x/driver/char directory, and modify the Makefile in the same directory, adding Obj_y += hpi.o to ../linux-2.4.x/driver/char/Makefile

At the same time, in order to automatically initialize this character device when Clinux starts, you also need to modify the ../linux-2.4.x/driver/char/men.c file and add the following:

(1) Newly added character driver initialization function declaration: extern void hpi_init(void);

(2) Call the initialization function of the new device in the unified initialization function of the character device int _init chr_dev_init(void). You need to add the statement: hpi_init();

In the function int _init chr_dev_init(void), the initialization function of the character device will be called uniformly and the registration of the character driver file_operations data structure will be completed. After initialization, the HPI character device can be used.

The data transmission bus converter designed in this paper not only solves the signal distortion problem caused by long transmission distance, but also meets the real-time requirements of information transmission. It also has gateway function and embedded Web function, which can ensure the safe access of the system to the Internet.