Design of Linear CCD Diameter Measurement System Based on ARM and FPGA

In recent years, the demand for products such as wires, cables, and optical fibers has greatly increased, and the quality control of outer diameter dimensions has become an urgent problem for many manufacturers. The traditional testing methods are as follows: (1) Manual measurement method: the method of first processing and then measuring is adopted, with average accuracy, many human factors, high labor intensity, and slow information feedback, which directly affects the quality of wires and production efficiency. (2) Contact measurement method: high accuracy, but easy to wear, and poor repeatability. (3) Photodiode array measurement method: fast speed, easy to handle, but poor accuracy. Therefore, a high-precision real-time online detection system is necessary. On the one hand, it can enable production personnel to understand the size and deviation of the wire diameter in a timely manner, and on the other hand, it can provide feedback proportional to the deviation to the production mechanism servo system to achieve feedback control. The dynamic outer diameter measuring instrument with linear array CCD high-precision sensor as the core has the advantages of fast speed, high accuracy, and strong anti-interference ability [1], becoming one of the most ideal industrial online detection methods.

1 CCD diameter measurement principle

Charge-coupled devices (CCDs) are new semiconductor integrated optoelectronic devices developed in the early 1970s. Currently, CCD technology has developed into a new technology with broad application prospects and has become one of the most popular research hotspots in modern optoelectronics and testing technology.

The principle diagram of the linear array CCD diameter measurement system is shown in Figure 1. In the figure, 1 is the light source; 2 is the lens, which is used to gather light energy; 3 is a piece of frosted glass, which is used to make the light as evenly distributed as possible; 4 is the cable to be measured; and 5 is the linear array CCD sensor to be imaged on it. The principle of cable diameter measurement is as follows: the light emitted by the light source 1 is corrected into approximately parallel light after passing through a series of lenses 2. When the light passes through the cable from the frosted glass 3, it is imaged on the photosensitive surface of the linear array CCD through the imaging objective lens, and finally the charge is converted into a voltage output through the output circuit of the CCD.

The CCD outputs a video pulse signal, in which each discrete signal corresponds to the output of a photosensitive unit on the CCD. At the same time, the CCD video signal needs to be converted into a standard signal by a processing circuit for further processing. When measuring the diameter of a cable, since no light passes through the blocked part of the cable, the diameter of the cable is proportional to the total length of the photosensitive unit minus the length of the photosensitive unit through the gap. The diameter of the cable can be measured according to the magnification (reduction) multiple of the imaging objective lens.

The calculation formula for the diameter of the cable under test is:
D=(L-hn)/β (1)
where L is the total length of the CCD effective measurement photosensitive unit, h is the pulse interval of the photosensitive unit, n is the number of photosensitive units passing through the gap, and β is the magnification of the imaging objective lens.

Therefore, as long as n is measured, the diameter of the measured cable can be calculated.

2 System Hardware Design

The hardware structure diagram of measuring cable diameter is shown in Figure 2. The embedded microprocessor LPC2214 produced by NXP is selected as the controller, which can meet the cable production industry's requirements for real-time, high-speed and accurate measurement and control of cable diameter. It also has the characteristics of high performance, low power consumption and low price, rich on-chip resources, and extremely high integration, supporting industrial-grade applications.

Since the photoelectric characteristics of CCD photoelectric sensors, such as conversion efficiency and signal-to-noise ratio, can only reach the optimal values ​​specified in the design and output stable and reliable signals under appropriate timing drive, the system uses FPGA chip (A3P030 from Actel) to design the CCD drive circuit.

2.1 Design of the main control module

The ARM embedded processor is the core of the entire hardware system. LPC2214 integrates a wealth of on-chip functional modules, including: external memory control module (EMC), system control module, universal parallel I/O port, serial communication port (UART), I ² C interface, SPI interface, CAN bus controller, timer control module, pulse width modulator, A/D converter, real-time clock controller, etc. LPC2214 integrates Flash memory and static RAM, of which Flash memory can be used as code and data storage.

After the tested cable in the system is evenly illuminated, it is imaged on the linear array CCD sensor at a certain magnification by the optical imaging system. Under the action of the driving pulse, the linear array CCD converts the collected light signal into an electrical signal output, and sends the processed analog video signal to the A/D converter. The role of LPC2214 is: when all the image-sensitive unit signal conversions are completed, the A/D device stops working, and an interrupt signal is given to the ARM microprocessor LPC2214, notifying LPC2214 to read all the data in the SRAM into the data storage through the data bus. The processor LPC2214 processes all the data according to the data processing program, and outputs the processing results to the LCD display through the data bus, which is convenient for real-time monitoring and subsequent control.

2.2 Design of CCD driving circuit

The design of CCD drive circuit is a key issue in the cable diameter measurement system. The drive circuits of CCD devices of different manufacturers and models are different, and the drive circuits of finished CCDs are expensive and inconvenient to use and promote [2]. This design uses Actel's FPGA device A3P030 and a CCD dedicated driver to form the CCD drive circuit. Experiments have shown that this circuit can reliably drive the CCD.

2.2.1 Timing requirements of TCD1501D

According to the technical requirements of the project, this system uses the TCD1501D linear array CCD of Japan's TOSHIBA company as the sensor. This device has excellent photoelectric characteristics and has 5,000 pixels. According to the timing of the CCD drive signal [3], TCD1501D requires six drive signals, which are: two clock pulses Φ1 and Φ2, transfer pulse SH, reset pulse RS, clamp pulse CP, and sampling pulse SP. TCD1501D works in a two-phase drive pulse mode. The drive frequency selected in the design is its typical value: f _Φ1 =f _Φ2 =0.5 MHz, and the corresponding data output frequency is fRS = 1 MHz. The signal output by the CCD device in one row is 5076 pixels, including 13 dummy unit signals, 48 ​​dark signal pulses, then effective pixel unit signals from S1 to S5000, 9 dark signal pulses, 2 parity detection signals and 1 dummy signal. After that, there can be any number of empty drives, so TSH≥5076TRS. Therefore, the shortest time required for each light integration can be calculated as: TSH≥5076TRS=5076?滋s=5.076 ms. According to relevant technical data [3], the six driving pulses of TCD1501D need to meet a specific timing relationship: Φ1 and Φ2 must be inverted, with a duty cycle of 1:1; the high level of SH must be maintained for at least 500 ns, its pulse width must be less than Φ1, and the delay must be at least 100 ns; the duty cycle of RS and CP clocks is 1:4.

2.2.2 TCD1501D drive circuit design

The structure of the driving circuit is shown in Figure 3. In this design, the FPGA programmable logic device A3P030 is responsible for generating six-way driving signals for the linear array CCD device TCD1501D. The chip has 30,000 system gates and is based on the Flash architecture. It is a low-power, non-volatile FPGA that is powered off. It can form a minimum system with a power supply, crystal oscillator, and reset circuit. The I/O port voltage of A3P030 is 3.3 V, and its maximum output low level VOL=0.4 V and minimum output high level VOH=2.4 V. The linear array CCD sensor TCD1501D requires a minimum input high level VIL=4.5 V. Therefore, the levels between the two devices do not match and cannot directly drive the CCD to work. Here, the level converter SN74ALVC4245 is used for level conversion, and then adjusted by the CCD dedicated driver chip to finally obtain a reliable driving signal. This circuit has a simple structure and good anti-interference performance. At the same time, it also has the advantages of low power consumption, high precision, and accurate timing coordination.

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2.3 A/D conversion circuit design

After the CCD image sensor completes the conversion of the photoelectric signal, in order to store and process the collected signals, they need to be converted into corresponding digital signals, which requires A/D conversion of the CCD output signal. Since the output frequency of the video signal of TCD1501D is 1 MHz, the speed of the general A/D converter cannot meet this requirement, so a high-speed A/D converter must be used. AD9243 is a full 14-bit high-performance analog-to-digital converter produced by Analog Devices, Inc. of the United States. Under a single +5 V power supply, its power consumption is only 110 mW, and the signal-to-noise ratio is ±79 dB. It also has a signal overflow indicator bit and can directly output data in binary form. Its data output port can be configured as 3 V or 5 V CMOS level, which is convenient for interfacing with various processors [4].
The function of AD9243 is to convert the analog video signal collected by the linear array CCD sensor into a digital signal and send it to the ARM microprocessor for calculation and storage of the cable diameter. In the design of the A/D conversion circuit, it is important to note that AD9243 can use different circuit designs in internal reference and external reference modes to obtain a flexible analog input range [4]. This design uses an external 2.5 V reference input, as shown in Figure 4.

This system uses a high-precision 2.5 V reference source as a stable external reference source. When using the external reference method, a capacitor decoupling network should also be added between CAPT and CAPB.

2.4 Human-machine interface module

In order to facilitate user management and operation, a parameter display and setting module for cable diameter measurement control is added. The ARM microprocessor LPC2214 is connected to the LCD display module LM057QC1T01 through the parallel port, and communicates with the touch screen module (controller is ADS7843) through the SPI serial interface built into the LPC2214. The parameters that can be set through the touch screen include: nominal value of diameter, upper tolerance, lower tolerance, PID parameters, etc. Correctly setting the nominal value of the cable diameter according to the process requirements can realize automatic feedback control and out-of-tolerance alarm of the cable diameter. When the system fails, the LCD display can display the system failure in time, which is convenient for users to eliminate it in time, and improves the efficiency of management and operation of production equipment.

3 Software Design

The data acquisition and data processing program in the microprocessor LPC2214 is the key part of the whole system. After the system initialization work is completed, the CPU starts to perform calculation processing. In the design, data acquisition and processing are performed in frames. The single frame reading and recognition process is as follows:
(1) LPC2214 sends a frame start pulse ena to FPGA.
(2) FPGA receives the ena signal, generates a CCD drive signal and a sampling signal of the A/D converter, and starts the CCD and A/D converter to work.
(3) The sampled digital signal is stored in SRAM.
(4) When a frame of data is collected, the INT signal is sent to ARM LPC2214, and ARM reads the SRAM and processes the data. The collection and processing process of a frame of data is completed, and if there is new data, it will continue to be processed. Figure 5 is the data processing software flow chart.

In the data processing program, after the A/D conversion is completed, LPC2214 reads the image data from the SRAM and stores it in the on-chip data storage space. First, the data is preprocessed, that is, the burrs in the waveform are filtered out and the values ​​that are impossible to appear in actual applications are eliminated. Then the preprocessed data is compared with the predetermined threshold. If it is higher than the threshold, the value in the high-order register is increased by 1, otherwise the value in the low-order register is increased by 1. After all 5,000 values ​​are compared, the value in the low-order register is calculated using the linear fitting method [5] to calculate the precise number of image-sensitive units in the linear array CCD that are blocked and unable to sense light. According to formula (1), the actual size of the measured cable diameter can be calculated.

This system replaces the traditional single-chip microcomputer with a high-speed ARM microprocessor and gives full play to the timing advantage of FPGA, making the system hardware structure simpler and more reliable, and software debugging more convenient. Compared with the previous acquisition system, the speed and accuracy have been greatly improved, fully meeting the requirements of system design. This system is for online measurement of cable diameter, but it is also suitable for measuring the length of workpieces, distance measurement and many other aspects, and has a broad application prospect.