ARM9 interrupt controller

Briefly review the control process of the ARM9 interrupt controller:

1. First, the triggered interrupt can be identified (the corresponding interrupt source must be turned on, and then the current interrupt status register is queried). The hardware will control the PC to jump to the interrupt vector entry (IRQ_HANDLE, as long as the hardware controls the IRQ interrupt type, it will enter), save the scene in the interrupt jump function (save R0 and other working registers) - jump to the service function (in which the interrupt source is judged and processed) - restore the scene. The basic process is as follows.

2. Interrupt triggering: high and low levels, rising and falling edges, etc., specifically set registers to achieve it.

3. Can the interrupt be transmitted to the CPU? After being triggered, it needs to pass through many switches (register settings to enable or not) to ensure that it reaches the CPU, so that the CPU can recognize it (some interrupt sources are not necessary). Some interrupts are secondary interrupts and require more switches. Pay attention to the chip manual.

4.

For example, we want to trigger the secondary interrupt signal INT_TC. OK, then what is the switch we want to turn on? In the secondary interrupt signal, INTSUBMSK is the switch of the secondary interrupt signal. We need to find the INT_TC bit in it and set it to 1. The secondary interrupt still needs to be transmitted to the primary central controller for processing. So we first find out which primary interrupt signal INT_TC belongs to. The purple frame in the table is the secondary signal belonging to the same primary signal. The primary signal processing also has a purple frame. INT_ADC is the corresponding primary signal we want to find. And it also has a corresponding switch, which is the controller INTMSK. We set the INT_ADC bit in INTMSK to 1 and it is considered successful.

The code is  

INTSUBMSK |= ( 0x1 << 9); //Because INT_TC is the 9th bit in INTSUBMSK, note that it starts from 0

INTMSK |= (0x1 << 31); // INT_ADC is bit 31 in INTMSK.

The same is true for other similar external interrupts. Only the first-level interrupt can be directly processed by the first-level central controller, so only the corresponding switch of the first-level central controller is set. In other words, we only need to turn on the corresponding switch of the device interface we want to use, and let ARM handle the rest.

5. EIN4_7 belongs to the first-level interrupt source, but this interrupt source contains four sub-interrupt sources: EIN4\EIN5\EIN6\EIN7.

SRCPND source pending register.

When the interrupt source sends a request, the processor will automatically set the corresponding bit of the register to 1.

Note: According to Samsung documents, this bit is not affected by the register, which is a mask register. When executing the service program, this bit must not be cleared, otherwise it will cause continuous interrupts. The clearing method is to write 1 to this bit.

 INTMOD interrupt mode register

This register determines whether the interrupt source is a FIQ interrupt or an IRQ interrupt.

Note: According to Samsung documentation, the INTPND register and INTOFFSET register are only valid for IRQ mode.

 INTMSK Interrupt Mask Register

Decide whether to mask an interrupt source

Note: No

 PRIORITY priority register

Determines the interrupt source priority.

 INTPND interrupt service routine flag

According to the document, when the interrupt source is not blocked and is waiting for interrupt service, the highest priority is set to 1. What this means is that the corresponding position of the register is 1, indicating that the CPU has responded to the corresponding interrupt request.

Note: Like SRCPND, the corresponding bit must be cleared in the interrupt service routine.

 INTOFFSET Register

This register is used in conjunction with INTPND. It indicates the value of the INTOFFSET register that corresponds to the IRQ interrupt in the INTPND register.

Note: Clear bit is also required

 SUBSRCPND Register

This register is used in conjunction with the .SRCPND register. When the sub-interrupt source issues a request, the processor will automatically set the corresponding bit of this register to 1.

 INTSUBMSK Register

This register is the same as the INTMSK register, except that it is relative to the sub-interrupt.

6. Borrowing pictures from other websites

 The dark black ones are the registers used for programming, and the light black registers are the flag registers generated by the CPU based on the registers we configured.

7. Finally, I feel that it is quite similar to 51. Set the pin as external interrupt (some are internal interrupts), enable, determine the priority, identify the trigger, save the scene, process, and restore the scene. The embedded Linux program needs to be organized together with the assembly. I am not very familiar with it at present. Learning ing~