s3c6410_clock initialization

refer to:

1) "USER'S MANUAL-S3C6410X" Chapter 3 SYSTEM CONTROLLER

2) u-boot/board/samsumg/smdk6410/lowlevel_init.S

1. Relationship between PLL and CLK:

For a detailed relationship diagram, see Figure 3-2 The block diagram of clock generator on page 122 of the user manual.

Three types of PLL: APLL, MPLL, EPLL

Four CLKs: ACLK, HCLK, PCLK

1) APLL generates ACLK, which provides the clock for the CPU;

2) In synchronous mode, APLL generates HCLK/PCLK, and in asynchronous mode, MPLL generates HCLK/PCLK. HCLK provides clock for peripherals on AXI/AHB bus, and PCLK provides clock for peripherals on APB bus.

3) EPLL mainly provides clock for audio-related peripherals;

2. Clock initialization steps

Assume our target clock size is:

ACLK: 532M

HCLK: 133M

PCLK: 66.5M

1) Set synchronous/asynchronous mode

Register: OTHERS

Address: 0x7E00F900

method:

Synchronous mode: Set bits [7][6] to 11, and wait for bits [11:8] to become 1111;

Asynchronous mode: Set bits [7][6] to 00 and wait for bits [11:8] to become 0000;

2) Set the lock time of each PLL

register:

APLL_LOCK

MPLL_LOCK

EPLL_LOCK

address:

0x7E00F000

0x7E00F004

0x7E00F008

method:

Set the lock time of the three PLLs to the maximum value 0xffff.

3) Set the frequency division coefficient of each CLK

register:

CLK_DIV0

address:

0x7E00F020

method:

The relationship between the output frequency, input frequency, and frequency division coefficient of each CLK is as follows:

In order to obtain the expected frequency (532_133_66), each RATIO takes the following values:

#define PCLK_RATIO 3 //PCLK=266M/(3+1)=66.5M

#define HCLKX2_RATIO 1 //HCLKX2=532/(1+1)=266M

#define HCLK_RATIO 1 //HCLK=266/(1+1)=133M

#define MPLL_RATIO 1

#define ARM_RATIO 0 //ACLK=532M/(0+1)=532M

#define CLK_DIV0_VAL

((PCLK_RATIO<<12)|(HCLKX2_RATIO<<9)|(HCLK_RATIO<<8)|(MPLL_RATIO<<4)|(ARM_RATIO))

4) Set the output frequency of each PLL

register:

APLL_CON

MPLL_CON

EPLL_CON0

EPLL_CON1

address:

0x7E00F00C

0x7E00F010

0x7E00F014

0x7E00F018

method:

(1) APLL/MPLL

There are three parameters in APLL_CON/MPLL_CON: MDIV, PDIV, and SDIV, which together determine the output frequency of APLL/MPLL:

FOUT = MDIV * FIN / (PDIV * 2^SDIV)

Common combinations of FIN, FOUT, MDIV, PDIV, SDIV are as follows:

Here we want to generate 533M APLL/MPLL, so the values ​​of MDIV, PDIV, and SDIV are as follows:

#define APLL_MDIV 266

#define APLL_PDIV 3

#define APLL_SDIV 1

#define APLL_CON_VAL ((1<<31)|(APLL_MDIV<<16)|(APLL_PDIV<<8)|(APLL_SDIV))

#define MPLL_MDIV 266

#define MPLL_PDIV 3

#define MPLL_SDIV 1

#define MPLL_CON_VAL ((1<<31)|(MPLL_MDIV<<16)|(MPLL_PDIV<<8)|(MPLL_SDIV))

(2) EPLL

The four parameters in EPLL_CON0 and EPLL_CON1: MDIV, PDIV, SDIV, KDIV jointly determine the output frequency of EPLL:

FOUT = (MDIV + KDIV / 2^16 ) * FIN / (PDIV * 2 ^SDIV)

Common combinations of FIN, FOUT, MDIV, PDIV, SDIV, KDIV are as follows:

Here we want to generate 96M EPLL, so the values ​​of MDIV, PDIV, SDIV, and KDIV are as follows:

#define EPLL_MDIV 32

#define EPLL_PDIV 1

#define EPLL_SDIV 2

#define EPLL_KDIV 0

#define EPLL_CON0_VAL ((1<<31)|(EPLL_MDIV<<16)|(EPLL_PDIV<<8)|(EPLL_SDIV))

#define EPLL_CON1_VAL (EPLL_KDIV)

5) Select the clock source

register:

CLK_SRC

address:

0x7E00F01C

method:

We select the output of the PLL as the clock source and set the lower three bits of CLK_SRC to 111.

3. Assembly code implementation of clock initialization

clock.S

/*

ACLK: 532M

HCLK: 133M

PCLK: 66M

*/

#include "clock.h"

.global clock_init

clock_init:

ldr r0, =ELFIN_CLOCK_POWER_BASE

/*step1: set synchronous mode*/

ldr r1, [r0, #OTHERS_OFFSET]

mov r2, #0x40

orr r1, r1, r2

str r1, [r0, #OTHERS_OFFSET]

nop

nop

nop

nop

nop

mov r2, #0x80

orr r1, r1, r2

str r1, [r0, #OTHERS_OFFSET]

check_syncack:

ldr r1, [r0, #OTHERS_OFFSET]

mov r2, #0xf00

and r1, r1, r2

cmp r1, #0xf00

bne check_syncack

/*step2: set pll lock time*/

mov r1, #0xff00

orr r1, r1, #0xff

str r1, [r0, #APLL_LOCK_OFFSET]

str r1, [r0, #MPLL_LOCK_OFFSET]

str r1, [r0, #EPLL_LOCK_OFFSET]

/*step3: set clk divider ratio*/

ldr r1, [r0, #CLK_DIV0_OFFSET]

bic r1, r1, #0xff00

bic r1, r1, #0x00ff

ldr r2, =CLK_DIV0_VAL

orr r1, r1, r2

str r1, [r0, #CLK_DIV0_OFFSET]

/*step4: set pll output frequency*/

ldr r1, =APLL_CON_VAL

str r1, [r0, #APLL_CON_OFFSET]

ldr r1, =MPLL_CON_VAL

str r1, [r0, #MPLL_CON_OFFSET]

ldr r1, =EPLL_CON0_VAL

str r1, [r0, #EPLL_CON0_OFFSET]

ldr r1, =EPLL_CON1_VAL

str r1, [r0, #EPLL_CON1_OFFSET]

/*step5: set clk src*/

ldr r1, [r0, #CLK_SRC_OFFSET]

mov r2, #0x7

orr r1, r1, r2

str r1, [r0, #CLK_SRC_OFFSET]

/*wait at least 200us to stabilize all clocks*/

mov r1, #0x10000

1: subs r1, r1, #1

bne 1b

mov pc, lr

4. Experimental Verification

Write a bare-metal program for a running light, and compare the flashing speed of the running light with and without clock initialization.

The frequency comparison is as follows:

When the clock is not initialized, the default CPU frequency is 400M.

After clock initialization, the CPU frequency is 532M.

Therefore, when the clock is initialized, the flashing speed of the running light should be faster.