1. Writing the bootloader for s3c24x0 - Introduction, watchdog and clock settings

1.1 Introduction

1.1.1 The role of the bootloader

The ultimate function of the bootloader is to start the kernel.

• From the above, we can know the simplest steps of writing uboot:

• Initialize hardware: turn off watchdog, set clock, set SDRAM, initialize nandflash

• If the bootload is large, relocate it to SDRAM

• Read the kernel from nandflash to SDRAM

• Set kernel boot parameters

• Jump execution kernel

1.1.2 norflash startup

Norflash can be read like RAM, but cannot be written like RAM.

1.1.3 nandflash boot

1.2 Watchdog and clock settings

1.2.1 Watchdog settings

2440 The watchdog must be turned off during startup, otherwise the chip will be restarted after a period of time.

The Watchdog Timer Control (WTCON) register allows the user to enable or disable the watchdog timer, select the clock signal from 4 different sources, enable or disable interrupts and enable or disable the watchdog timer output. The watchdog timer is used to recover the S3C2440 after power-on if there is a fault and restart; if you do not want the controller to restart, you should disable the watchdog timer.

If the user wants to use the watchdog timer as a normal timer, the interrupt should be enabled and the watchdog timer should be disabled.

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1.2.2 Clock Settings

The clock control logic in S3C2440 can generate the necessary clock signals, including FCLK of CPU, HCLK of AHB bus peripherals and PCLK of APB bus peripherals. S3C2440A contains two phase-locked loops (PLL): one for FCLK, HCLK and PCLK, and the other for USB module (48MHz).
The clock control logic can not use PLL to slow down the clock, and the clock of each peripheral module can be connected or disconnected by software to reduce power consumption.

The selection of clock source is related to the startup mode. When booting, the clock source selection is as follows:

• FCLK, HCLK and PCLK

• FCLK is the clock provided to ARM920T.

• HCLK is the clock provided to the AHB bus used for ARM920T, memory controller, interrupt controller, LCD controller, DMA and USB host modules.

• PCLK is the clock provided to the APB bus for peripherals such as WDT, IIS, I2C, PWM timer, MMC/SD interface, ADC, UART, GPIO, RTC and SPI.

• S3C2440 supports the selection of the frequency division ratio between FCLK, HCLK and PCLK. The ratio is determined by HDIVN and PDIVN in the CLKDIVN control register.

For S3C2440, the chip manual has this paragraph that needs attention:

We have to change the CPU bus mode to asynchronous bus mode.

As mentioned above, the S3C2440A contains two phase-locked loops (PLL): one for FCLK, HCLK and PCLK, and another dedicated to the USB module (48MHz).

Therefore, a phase-locked loop must be set to provide clock sources for FCLK, HCLK and PCLK:

UPLL is provided for USB use. We need to set MPLL. For MPLLCON, you can set it according to the table provided in the chip manual:

• Input frequency: input clock source, external 12M crystal oscillator, schematic design

• Output Frequency: Output clock source, that is, MDIV. If 400M is selected, the MDIV value is 0x5c.

1 #define CLKDIVN 0x4C000014 /** Clock division control register*/

2 #define MPLLCON 0x4c000004

3 #define S3C2440_MPLL_400MHZ ((0x5c<<12)|(0x01<<4)|(0x01)) /** 400M clock source*/

4

5 /** 3. Chip manual requires:

6 * If HDIVN is not 0, the CPU bus mode should be changed from fast bus mode to asynchronous bus mode */

7 mrc p15, 0, r1, c1, c0, 0 /* Read control register */

8 orr r1, r1, #0xc0000000 /* Set to asynchronous bus mode */

9 mcr p15, 0, r1, c1, c0, 0 /* Write control register */

10

11 /** 4. Set clock frequency */

12 ldr r0, =MPLLCON

13 ldr r1, =S3C2440_MPLL_400MHZ

14 str r1, [r0]

15

16 /** 5. Initialize SDRAM */

17 mov ip, lr /** Save the current program address to the ip register*/

18 bl sdram_init /** Execute SDRAM initialization */

19 mov lr, ip