S3C2440 memory status when booting from NAND FLASH or NOR FLASH

1. When booting from NANDFLASH, when ARM is powered on, ARM will automatically copy the first 4K of NANDFLASH to the S3C2440 internal SRAM, and map the address of SRAM to 0X00000000. After ARM is powered on, it will start running from SRAM.

2. When booting from NOR FLASH, because NORFLASH is connected to bank0, the address mapping is 0X00000000. So after ARM is powered on, it directly runs the program in NORFLASH. At this time, the internal SRAM address of S3C2440 is 0X40000000.

3. ARM starts from 0X00000000 when powered on. However, for the reset program entry, the value of ResetEntry is 0X00000000 when ARM is powered on, and 0X30000000 in JTAG simulation. This value is critical and will be used when copying the program.

The hardware determines whether to boot from nand flash or nor flash when booting. The specific configuration is as follows

Then, the corresponding memory mapping is as follows

SROM means ROM or SRAM type memory

Regarding Figure 6-5, the following explanations are required:

1. On the jz2440 development board, SDRAM is connected to BANK6, and its starting address is always 0x30000000.

2. The column diagram shown in the figure is the memory that the chip considers. That is, it can be considered as the memory inside the chip.

3. For booting from nand flash with OM[1:0]=00, nand flash cannot unify the address to memory. After power-on, the chip automatically copies the first 4k of nand flash to the first 4k of memory in the chip, and then the chip starts to run from 0x00000000. The 4k memory content copied from 0x00000000 is responsible for copying the bootloader in nand flash to the chip address 0x30000000. When continuing to execute, BANK1, BANK2,, are not connected to SROM, so the code at 0x30000000 will be executed immediately. The whole process can be said that the 4K code copied to the SRAM inside the chip copies the program in nand flash, including the bootloader, to the link address (the link address is the SDRAM address), and then executes sequentially.

4. For OM[1:0]=01, 10, it is started from the nor flash. The nor flash is connected to BANK0, which exists as the SROM here. Its starting address is 0x00000000, and the chip executes sequentially from address 0.