Simple and easy-to-understand startup process of uboot

static ulong get_PLLCLK(int pllreg)

{

    S3C24X0_CLOCK_POWER* const clk_power = S3C24X0_GetBase_CLOCK_POWER();

    ulong r, m, p, s;

    if (pllreg == MPLL)

    r = clk_power->MPLLCON;

    else if (pllreg == UPLL)

    r = clk_power->UPLLCON;

    else

    hang();

    m = ((r & 0xFF000) >> 12) + 8;

    p = ((r & 0x003F0) >> 4) + 2;

    s = r & 0x3;

  if(gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)

    return((CONFIG_SYS_CLK_FREQ * m) / (p << s));

  else 

      {

// return ((CONFIG_SYS_CLK_FREQ * m * 2)/(p<          return (CONFIG_SYSPLL_CLK_FREQ/(p<       }

}

Pay attention here

return ((CONFIG_SYS_CLK_FREQ * m * 2)/(p<
return (CONFIG_SYSPLL_CLK_FREQ/(p<
process:
      1. The first thing to execute is the outermost makefile of the uboot folder. Compile make XXXX_Config, and a setting file for this platform will appear in the include/config folder. This uboot can be trimmed. Then execute make all to compile and connect.
      2. After completing 1, please look at start.S under the CPU folder. The assembler of this file will perform the following functions: 1. Turn off the watchdog, 2. Enable SDRAM 3. Code relocation, allocate stack, global variables, and interrupts Space. Then call the C file (board.c) under the board folder, which will contain various initialization programs.
        Makefile_Uboot => CPU.Start.S=>lib/arm=>start_armboot=>board/makefile=>board.c
 
Note include 
Here are the steps for compatibility with the 2440:
1. Modify the overall make file so that it can execute make 100ask24x0_Config (_config can be named as you like)
100ask24x0_config : unconfig 
@(MKCONFIG)(MKCONFIG)(@:_config=) arm arm920t 100ask24x0 NULL s3c24x0
 
2. Assign smdk2410 in the board directory and change the name to 100ask24x0. The c file inside is also renamed to 100ask24x0.c
3. Copy a file called 100ask22X0.h in include/config/smdk2410.h, which contains some hardware settings.
 
 
4. Modify in board/100ask24x0/Makefile
 
 
 
5. Next, you need to change the SDRAM driver. This part of the program is in the lowlevel_init.S file. 
 
 6. Modify the clock
S3C2410 FCLK runs at 200Mhz and S3C2440 runs at 400Mhz, so our frequency division ratio should change from 1:2:4 to 1:4:8. We also set UPLL to 48Mhz, that is, UCLK is 48Mhz. 
Modify the board.c function of 100ask24X0.c
 
 
In addition the board_Init function needs to be changed
 
int board_init (void)
{
    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
    S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

    
    /* set up the I/O ports */
    gpio->GPACON = 0x007FFFFF;
    gpio->GPBCON = 0x00044555;
    gpio->GPBUP = 0x000007FF;
    gpio->GPCCON = 0xAAAAAAAAA;
    gpio->GPCUP = 0x0000FFFF;
    gpio->GPDCON = 0xAAAAAAAAA;
    gpio->GPDUP = 0x0000FFFF;
    gpio->GPECON = 0xAAAAAAAAA;
    gpio->GPEUP = 0x0000FFFF;
    gpio->GPFCON = 0x000055AA;
    gpio->GPFUP = 0x000000FF;
    gpio->GPGCON = 0xFF95FFBA;
    gpio->GPGUP = 0x0000FFFF;
    gpio->GPHCON = 0x002AFAAA;
    gpio->GPHUP = 0x000007FF;
    
  if((gpio->GSTATUS1 == 0x32410000)||(gpio->GSTATUS1 == 0x32410002))
   {

      clk_power->CLKDIVN = S3C2410_CLKDIV;

     _asm_( "mrc p15, 0, r1, c1, c0, 0n"
                   "orr r1, r1, #0xc0000000n"
                   "mcr p15, 0, r1, c1, c0, 0 n"
                   :::"r1"
     );

     clk_power->LOCKTIME = 0xFFFFFFFF;
     clk_power->MPLLCON = S3C2410_MPLL_200MHZ;

     delay(4000);

     clk_power->UPLLCON = S3C2410_UPLL_48MHZ;

     delay(8000);

     

    /* arch number of SMDK2410-Board */
    gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
   }
  else
      {
         clk_power->CLKDIVN = S3C2440_CLKDIV;
        

             _asm_( "mrc p15, 0, r1, c1, c0, 0n"
                   "orr r1, r1, #0xc0000000n"
                   "mcr p15, 0, r1, c1, c0, 0 n"
                   :::"r1"
     );

         clk_power->LOCKTIME = 0xFFFFFFFF;
     clk_power->MPLLCON = S3C2440_MPLL_400MHZ;

     delay(4000);

     clk_power->UPLLCON = S3C2440_UPLL_48MHZ;

     delay(8000);
        gd->bd->bi_arch_number = MACH_TYPE_S3C2440;
       }
    /* adress of boot parameters */
    gd->bd->bi_boot_params = 0x30000100;

    icache_enable();
    dcache_enable();

    return 0;
}

6. The following is to set the baud rate so that the serial port can work. The file is in the start_armboot function. This function will call the serial_init function. Related to this function are get_HCLK get_PLLCLK. These functions are in cpu/arm920t.s3c24x0/speed.c.
/*for S2c2440*/
#define S3C2440_CLKDIVN_PDIVN (1<<0)
#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
#define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
#define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
#define S3C2440_CLKDIV_UCLK (1<<3)

#define S3C2440_CAMDIVN_CAMCLK_MASK (0XF<<0)
#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
 #define S3C2440_CAMDIVN_DVSEN (1<<12)
/* return HCLK frequency */
ulong get_HCLK(void)
{
    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
    unsigned long clkdiv;
    unsigned long camdiv;
    int hdiv = 1;

    if(gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)
          return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
    else
        {
                clkdiv = clk_power->CLKDIVN;
          camdiv = clk_power->CAMDIVN;

          switch(clkdiv & S3C2440_CLKDIVN_HDIVN_MASK)
              {
                        case S3C2440_CLKDIVN_HDIVN_1:
                     hdiv = 1;
               break;
                   

                       case S3C2440_CLKDIVN_HDIVN_2:
                   hdiv = 2;
              break;

              case S3C2440_CLKDIVN_HDIVN_4_8:
                    hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
                  break;
            case S3C2440_CLKDIVN_HDIVN_3_6:
                hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF)? 6 : 3;
                break;
               }

                   return get_FCLK()/hdiv;
 
          }
}

/* return PCLK frequency */
ulong get_PCLK(void)
{
    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
    unsigned long clkdiv;
    unsigned long camdiv;
    int hdiv = 1;

    if(gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)
       return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
   else
       {
         clkdiv = clk_power->CLKDIVN;
      clkdiv = clk_power->CAMDIVN;
  
        switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK)
            {
                 case S3C2440_CLKDIVN_HDIVN_1:
                 hdiv = 1;
          break;
 
               case S3C2440_CLKDIVN_HDIVN_2:
               hdiv = 2;
        break;

        case S3C2440_CLKDIVN_HDIVN_4_8:
                       hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF)? 8 : 4;
        break;

        case S3C2440_CLKDIVN_HDIVN_3_6:
                       hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF)? 6 : 3;
        break;
        }
         return get_FCLK()/hdiv/((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2 : 1);
      }
}
The code inside is changed to hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF)? 6 : 3;
Note that CAMDIVN is not defined in clk_power, so you need to find it in include (S3C24x0.h) and add it again.
 
At this point, the first phase of uboot ends
 
Things accomplished in the first phase:
1. Set make config in the total Makefile
2. Change the compiled file in the Makefile
3. Change the clock in the board.c file
4. Change the clock to USART in the speed file
 
The second stage: select nor flash. The board we use supports AM29LV800 and the default is AM29LV800, so we need to change the config file.
Inside includeconfigs
 
I will verify whether the second stage is correct, and will update the subsequent process. So far, the u-boot transplantation is basically completed, but it only supports nor flash.
Nand flash content will be added later