Taking s3c2440 as an example to explain the startup process of the arm chip

The startup process of arm embedded chips is actually very complicated for embedded novices. Many people have only a little understanding of it and there are many misunderstandings. In the author's opinion, if you want to truly understand this startup process, you must first understand the differences and connections between memories. Please refer to the article: The Differences and Connections of Various Mainstream Semiconductor Memories. You also need to understand how the program is compiled, linked and executed.

This article will take s3c2440 as an example to describe the startup process of the arm chip in detail. s3c2440 supports two startup modes: NAND FLASH startup and non-NAND FLASH startup (usually NOR FLASH startup, and the data width can be configured), which is controlled through the two pins OM1 and OM0.

NAND FLASH startup process

When both OM1 and OM0 pins are low, the CPU is configured to start as NAND FLASH. At this time, the 4KB SRAM inside the CPU will be mapped to the nGCS0 space (the starting address is 0x00000000). When powered on, the CPU will automatically copy the first 4KB data in the NAND FLASH to the on-chip SRAM. Then the CPU starts executing the program from the 0x00000000 address of the internal SRAM, initializes the system accordingly, and prepares for subsequent program execution beyond 4Kb.

In other words, the programs that can be executed during the CPU startup process can only occupy up to 4Kb of space. If you need to execute more programs, you need to complete the initialization of DRAM in a 4Kb program (DRAM must be initialized before use), configure the stack space, copy the programs that need to be executed to DRAM, and then jump to DRAM. Continue execution.

The reason why the code in the NAND FLASH must be copied to the internal SRAM before execution during the startup process is because the NAND FLASH needs to be accessed through the NAND FLASH controller and cannot be directly accessed through the CPU bus, so the program cannot be executed.

NOR FLASH startup process

When the system is configured to start in this way, the CPU internal SRAM is no longer mapped to the address space. At this time, what is mapped to the nGCS0 (starting address is 0x00000000) address space should be the external NOR FLASH (memory that stores the startup code). ). When the system is powered on or reset, the CPU starts executing code directly from address 0x00000000 (which is the starting address of NOR FLASH). Compared with NAND FLASH startup, the NOR FLASH startup code can reach 128Mb (s3c2440).

The reason why code can be executed directly on NOR FLASH is because NOR FLASH has a RAM-like access interface and can directly perform random reads through the CPU bus, but does not support random write operations. Therefore, C language cannot be included in these startup codes. This is because the program must have variables (which need to be written) and require stack space to call functions (which also need to be written), and the assembler can avoid writing to the memory space. of.

So does that mean that if NOR FLASH is started, there cannot be a C program? Of course not, don't forget the existence of DRAM. When the NOR FLASH startup process completes the initialization of the DRAM and the configuration of the stack space, the C language program can be called.

This is the startup process of the arm chip. In fact, there are many places in the startup code at the beginning of the startup process that are worthy of careful consideration, and there will also be many questions. At this time, you should understand how the program is compiled and linked. , and how to implement it.