OK6410A Development Board (VIII) 56 linux-5.11 OK6410A armv6 Exception memory access exception

This article describes data abort and instruction fetch abort in armv6 exceptions

ARMv6 Exceptions

ARMv6 7 exceptions

reset and swi share SVC exception mode (privileged)

Data abort and instruction fetch abort share the ABT exception mode (privileged)

attempted execution of an Undefined instruction UND exception mode (privileged)

IRQ, normal interrupt IRQ abnormal mode (privileged)

FIQ, fast interrupt FIQ exception mode (privileged)

ARMv6 non-exceptional 2 types

user user mode (non-privileged)

system system mode (privileged)

Suspension

Suspension

During the memory access process, the ARM processor may have an exception

The cause of the exception is abort (abnormal access), which is divided into three types:

MMU faults (4 types)

The MMU detects the limitation and signals it to the processor.

Debug abort

Monitor debug mode is enabled and a breakpoint or watchpoint is detected.

External abort (three types)

The external memory system signals an illegal or erroneous memory access.

When an exception occurs, the relevant context information is recorded in register 5 and register 6.

The type of exception that caused the abort

What exception would the abort described in this article cause?

MMU faults

If the aborted memory request was an instruction fetch, a Prefetch Abort exception is raised when the processor attempts to execute the instruction corresponding to the aborted access.

If the aborted access is a data access or cache maintenance operation, a data abort exception is raised.

Debug event

When watch debug mode is enabled, execution can be aborted due to a breakpoint on instruction access, generating a prefetch abort exception

When watch debug mode is enabled, execution can be aborted due to a watchpoint on data access, generating a data abort exception

External abort

External abort during instruction fetch, may generate a prefetch abort exception (depending on whether it is executed)

External abort during data reading/writing will generate a data abort exception

External abort on hardware page table walk, generates data abort exception

Suspension of detailed interpretation

1.MMU faults

If the MMU detects an abort, no external accesses will be made to the address where the abort was detected.

Abnormal access source classification:

If the aborted memory request was an instruction fetch, a Prefetch Abort exception is raised when the processor attempts to execute the instruction corresponding to the aborted access.

Question: If the MMU detects an abort, no external access will be made to the address where the abort was detected, so the instruction was not prefetched successfully, how can it be attempted to execute???

See Exceptions on page A2-16 for details on prefetch aborts.

If the aborted access is a data access or cache maintenance operation, a data abort exception is raised.

See Exceptions on page A2-16 for more information on data aborts.

Faults check order

The order in which the MMU checks for access faults differs slightly between sections and pages.

Figure B4-2 on page B4-15 shows the order of the two access types.

The MMU generates four types of faults:

alignment fault

For details of when alignment faults are generated, see Table A2-10 on page A2-40

translation fault

There are two types of translation errors:

part

This is generated if the first level descriptor is marked invalid.

This happens when bits [1:0] of the descriptor are all 0;

or VMSAv6, the value of bit [1:0] of the descriptor is 0b11 (reserved value)

Page

This is generated if the second level descriptor is marked invalid.

This happens if bits [1:0] of the descriptor are all 0.

Will TLBs be flushed?

Page table entry (PTE) fetches that cause translation errors are guaranteed not to update the TLBs. 

Flushing corrupted entries when a translation error occurs does not require TLB maintenance operations.

domain fault

There are two types of domain failures:

Segment domain failure

Check the domain when returning a valid first level descriptor.

Page domain error

Check the domain when returning a valid second-level descriptor (based on the domain field of the first-level descriptor).

Will TLBs be flushed?

If a domain error results in an update to the associated page table, the corresponding TLB entry needs to be flushed to ensure correctness.

See the TLB Maintenance Operations and Page Table Entry Update Examples in the Memory Order Model on page B2-22 for more information.

Memory order model related

Changes to the domain access control registers are synchronized by the execution of a prefetch flush operation (or due to an exception or exception return).

See Changes to the CP15 Register and Memory Order Model on page B2-24.

permission fault

When to check:

If the two-bit field returns client (01), a permission access check is performed on the access permission field in the TLB entry.

Will TLBs be flushed?

If a permission error causes an update to the associated page table, the corresponding TLB entry needs to be flushed to ensure correctness.

See the TLB Maintenance Operations and Page Table Entry Update Examples in the Memory Order Model on page B2-22 for more information.

2.Debug event

When the suspension occurs:

When watch debug mode is enabled, execution can be halted due to a breakpoint on an instruction access or a watchpoint on a data access.

Breakpoint on instruction access

FSR is updated (instruction or data) to indicate debug abort // This is the only information saved on a prefetch abort (breakpoint) debug event

R14_abt is updated to determine the address of the failed instruction // This is an exact abort.

Watchpoint on data access

WFAR is updated for you to determine which instruction caused the debug event // The debugger must read the Watchpoint Fault Address Register (WFAR)

R14_abt cannot be used to determine the address of the failed instruction // The watchpoint is not precise because subsequent instructions can run under loads and stores

3. External abort

Who issued the suspension?

External memory errors are those errors that occur in the memory system and are not detected by the MMU.

Foreign memory errors are rare and can be fatal to a running process.

example

Uncorrectable parity or ECC failure on the L2 memory structure.

Implementation defined

It is implementation-defined which, if any, external abort is supported.

concept

Accurate: Hardware settings R14_abt is updated.

Updated registers

A precise external abort is signaled in the DFSR or IFSR.

See Inexact Data Abort on page A2-23 for more details on the inexact external abort model.

External abort on instruction fetch

The memory system sends a memory abort signal to the ARM processor, and the prefetched instructions are marked as invalid.

Is it accurate?

Externally generated errors during instruction prefetch are precise in nature

Will it cause an exception?

If the instruction is not executed, the prefetch instruction abort will not occur. // Example jumps in the instruction pipeline

A prefetch instruction abort occurs when the CPU attempts to execute an instruction fetched from a location that caused the fault.

Updated registers

Do not update the Fault Address register

External abort during data read/write

Externally generated errors during data reading and writing may be imprecise.

When entering the abort handler in the case of such an abort, there is no guarantee that the address associated with the instruction that caused the exception will be present in R14_abt.

Accordingly, external aborts may not be recoverable

1. Abort is not re-entry

If an imprecise external abort causes entry into the Abort state and the Abort state is not reentrant, the processor is in an unrecoverable state because the R14 and SPSR values ​​are corrupted.

2. The suspended state is re-entry

For this reason, the processor recognizes an imprecise external abort only when the abort state is re-entered.

This is managed by providing a mask in the CSPR for the imprecise external abort, called a bit.

Updated registers

Update DFSR // Indicates that there was an imprecise external abort.

Do not update FAR 

External abort on hardware page table walk

An external abort on a hardware page table access must return with the page table data. // What does this return mean??? 

Such a stop is precise.

Updated registers

Update FAR

Update FSR (instruction or data) // to indicate that this happened.

Parity Error Reporting

Is it accurate?

Parity errors can occur as exact (e.g., read from L1 cache hit) or imprecise (e.g., cache line fill) aborts.

What is defined

The architecture defines

1. Fault status codes used to report parity errors

Implementation Defined

1. What parity error support is provided?

2. Whether they are reported using specified fault status codes or other appropriate coding

This article mainly describes the classification of the causes of memory system-related exceptions (aborts), corresponding to data abort and instruction fetch abort sharing the ABT exception mode (privilege)

Flowchart of memory access exception

Figure B4-2 Sequence for checking faults