Principles of Single-Chip Microcomputers P0: 80C51 Structure Principles

　　 1. P1 port:

　　It can be seen that the P1 port is simpler than the P0 port. It is a quasi-bidirectional port, but it does not have the control circuit of the P0 port. Like P0, when inputting data, you must first write 1 to the P1 port, otherwise the input will be invalid (some of the following homework will cause many strange problems because of ignoring this issue.), the P1 port can drive any circuit (MOS, TTL...). Unlike the P0 port, the P1 port does not require a pull-up resistor when used as a standard output port.

　　 2. P2 Exit:

　　Port P2 is also a quasi-bidirectional port. When expanding external circuits, it forms a 16-bit address together with P0. Of course, port P2 can also be used for standard input and output.

　　 3. P3 Exit:

　　Port P3 is a quasi-IO port with similar functions to P1 and can be used as a standard IO port. However, port P3 has its unique functions as follows: For output special functions: the corresponding latch is automatically output as 1 by the CPU.

　　Note the RD and WR ports below; these two ports are used to expand external memory.

　　When P0~P3 ports are used as general input ports, the circuit latch must be written with 1.

　　It is necessary to distinguish between two ways of reading ports (reading latches and reading pins). Generally speaking, most operations of reading latches require reading and writing ports, while operations of reading pins generally only read ports without writing (reading pins will not affect the status of latches).

　　Each IO port of P0 can drive 8 LS TTL inputs, while each IO port of P1~P3 can only drive 4.

　　(Off topic: The number of drivers is actually very important, because in actual use, junk chips like 80c51 will cause continuous restarts (a "da da da da" sound will occur) due to too many drivers causing too much current. This kind of thing happened in my project. At that time, I had problems with too many white LEDs driven at a low level. I didn't know what was going on. Although I could add pull-up resistors, it would result in insufficient brightness. Finally, I changed to high-level drivers to solve the problem.)

5. 80C51 internal data memory (lower 128 bytes)

　　The internal memory of 80c51 is SRAM (256 bytes), the lower 128 bytes are the internal data RAM area, and the upper 128 bytes are the special function registers (SFR).

　　1. Working register group (00H - 1FH)

　　The lowest 32 bytes are registers. Each group of general registers has 7 8-bit registers R0-R7. The flag bits (RS0 and RS1 of the PSW register in the special registers) specify which group to use.

The assembly code is as follows (if you don't understand it, you can look at the instructions first):

MOV R0, #FFH ; Assume the register is currently 0

SETB RS0; Set RS0, that is, switch to register bank 1

LCALL SHIT ;Call a procedure

CLR RS0 ; switch back to register bank 0

SHIT:

MOV R0, #00H ; In the SHIT method, R0 is changed. At this time, the content of register group 1 is changed, and the content of R0 of register group 0 remains unchanged.

RIGHT

　　There are 16 bytes in total, or 128 bits. Note that this area can be operated on either bytes or bits, for example:

MOV A, 20H; operation is byte

MOV C, 20H; the operation is bit

　　3. User RAM area (30H - 7FH) There are 80 bytes in total, and these areas can be used at will.

6. 80C51 internal data memory (upper 128 bytes)

　　It should be noted that the 80c51 has a total of 22 dedicated registers, but the PC is a non-addressable register, so it does not belong to the SFR area. The other 21 are in the SFR area (which can be addressed (directly type the name), but not necessarily bit-addressable).

(Image source: http://pdf-file.ic37.com/pdf1/PHILIPS/PCB80C31BH3-16H_datasheet_146374/238405/PCB80C31BH3-16H_datasheet.pdf )

　　This is the picture in the 51 MCU manual (off topic: I actually recommend that you learn 51 by reading the manual and a reliable book. It is much more useful than watching those so-called 51 MCU teaching garbage videos. The picture in the book is actually a simplified version of the manual picture. For some special chips, such as the chip corresponding to the manual picture above, we can see that this chip has an additional IPH compared to the picture in the book (when I first started learning, I was very confused why 80C51 only has two priorities, 0 and 1. In fact, this is a design defect. The new 80c51 has this thing added). Of course, in order to cope with the exam, I still recommend that you pretend not to see this thing.)

　　The functions of the special registers above correspond to the English ones one by one. At the same time, the addresses of some registers above cannot be divided by 8 (such as the high 8 bits DPH and the low 8 bits DPL of DPTR). These registers are those that cannot be bit-addressed. Let's first talk about some special ones (other registers will be used later):

A register (Accounter): All ALU operation instructions must use A, the most frequently used register

PC register (Program Counter): This is a 16-bit register (maximum addressing range 64KB, range 0000H~0FFFFH), which always points to the address of the next instruction.

PSW (Program Status Word): This is an 8-bit register, from high to low, CY AC F0 RS1 RS0 OV (empty) P

The AC bit is the auxiliary carry flag: when the lower four bits of the operation result carry or borrow to the upper four bits, this flag is automatically set to 1 by the hardware (for example, the DA instruction above uses this flag);

F0 is the user flag: this thing is actually used to assist reset. This thing is somewhat related to the watchdog. The F0 flag can be combined with an external reset circuit.

RS0 and RS1 markers: Mark the register group currently in use.

P is the parity flag: it indicates whether the number of 1s in the result is even or odd.

The two flags CY and OV are very interesting.

CY is the carry flag of the highest bit. If there is a carry/borrow, CY=1, otherwise it is 0.

For addition and subtraction, the OV flag indicates whether the result of the operation exceeds -128~127. If so, it is set to 1, otherwise it is 0.

If it is a multiplication, then if it exceeds 255, OV is 1, and the results are stored in the A and B registers respectively; otherwise, it is 0, and the result is only stored in the A register.

If it is division, OV=1 means the divisor is 0, otherwise the divisor is not 0. If there is an odd number of 1s in the result A, set P=1; otherwise P=0. It is often used to check whether data transmission in serial communication is wrong.

An example question:

If: (A) = 78H, (R0) = 64H, after executing ADD A, R0, the result and PSW =?

       （A）：78H= 01111000 B

     + （R0）：64H= 01100100 B

       （A）：DCH= 11011100 B

Flag bit: CY=0, AC=0, OV=1, P=1, i.e. PSW=05H

Result: (A) = DCH (R0) = 64H

At this time, CY XOR OV is 1, indicating that the result overflowed (a quick way to check whether addition and subtraction have overflow).

DPTR register (Data Pointer): 16-bit register, which can be divided into DPH and DPL. Often used with MOVX and MOVC instructions.

SP Stack Pointer: Students who have studied data structures are very clear about this, so I will not explain it in detail. Just note that the stack of 80c51 grows upward, and a push instruction first adds 1 and then pushes in data, while a pop instruction first pops the data and then -1 the pointer.

We will talk about other registers later (TMOD, TCON, PCON...).

7. 80C51's internal program memory

　　When EA is high, the program starts with fetching instructions from the internal program memory at 0x0000. When the internal content exceeds 0xfff, the program goes to the external program memory to execute instructions. The external program memory is addressed from 0x1000. Of course, for the enhanced version, the contents of the external program memory will be executed only when the PC content exceeds 0x1fff.

　　When EA is tied low, the program fetches instructions directly from the external program memory, starting with addressing at 0x0000.

　　Some low-end addresses of the program memory are fixed for some specific entry addresses: 0x0000~0x0002 generally store jump instructions, followed by 8 interrupt entry addresses:

　　The units after 002BH are program memory units that can be used at will (a bit like the interrupt vectors in the front of 8086).