《2440 Bare Metal》Clock System

1. Principle Analysis

The S3C2440A has two phase-locked loops (PLLs): one (MPLL) for FCLK, HCLK and PCLK, and the other (UPLL) dedicated to USB. FCLK is used for CPU, HCLK is used for AHB bus, and PCLK is used for APB bus.

AHB (Advanced High performance Bus) is an advanced high performance bus used to connect high performance modules.

APB (Advanced Peripheral Bus) peripheral bus, used for connecting low-speed peripherals.

After simplifying the above picture, we can roughly get the following picture.

From this simplified diagram, we can see that the frequency of the crystal oscillator generated by MPLL is the frequency used by FCLK, and the frequency generated by UPLL is the frequency used by USB. If FCLK is further divided by HDIV and PDIV, HCLK and PCLK will be obtained respectively.

So what is the entire timing and workflow from system power-on (reset) to working at the set frequency? There is a diagram in the chip manual that explains this process.

After the system is powered on, the crystal oscillator (OSC) starts working. After the OSC is stable, nRESET will be pulled to a high level, and then the PLL will work according to the configuration. After the lock time, FCLK can be immediately configured as the phase-locked loop output.

With the above theoretical basis, if we want to set FCLK:HCLK:PCLK=400M:100M:50M and the crystal frequency is 12M, we can divide the configuration into the following steps:

Set LOCKTIME (0x4C000000)

Set the division value of HDIV and PDIV, FCLK:HCLK:PCLK=400M:100M:50M, so we can get HDIV=4, PDIV=8. These two values ​​can be configured through the CLKDIVN (0x4C000014) register.

According to the table above, HDIVN should be configured as 0b10, PDIVN should be configured as 0b1, so this register should be configured as 0x5

Set the CPU to work in asynchronous mode

The general meaning of this paragraph is that if HDIVN is not 0 (we set it above, it is indeed not 0), the CPU mode must be changed from fast bus mode to asynchronous bus mode. How to change it? The chip manual also provides assembly code. The question is what does #R1_nf:OR:R1_iA mean?

In fact, orr r0,r0,#R1_nf:OR:R1_iA means to set bit 30 (nf bit) and bit 31 (ia bit) to 1, so this sentence is equivalent to orr r0,r0,#0xc0000000

Set P, M, S in MPLL to make FCLK=400M

The manual provides a formula. Now we can substitute the values ​​given in the manual into the formula to verify it.

The values ​​of these three can be set through MPLLCON (0x4C000004).

2. Programming

.text

.global _start

_start:

/* Disable watchdog */

ldr r0, =0x53000000

ldr r1, =0

str r1, [r0]

/* Set MPLL, FCLK : HCLK : PCLK = 400m : 100m : 50m */

/* LOCKTIME(0x4C000000) = 0xFFFFFFFF */

ldr r0, =0x4C000000

ldr r1, =0xFFFFFFFF

str r1, [r0]

/* CLKDIVN(0x4C000014) = 0X5, tFCLK:tHCLK:tPCLK = 1:4:8 */

ldr r0, =0x4C000014

ldr r1, =0x5

str r1, [r0]

/* Set the CPU to work in asynchronous mode */

mrc p15,0,r0,c1,c0,0

orr r0,r0,#0xc0000000 //R1_nF:OR:R1_iA

mcr p15,0,r0,c1,c0,0

/* Set MPLLCON(0x4C000004) = (92<<12)|(1<<4)|(1<<0) 

* m = MDIV+8 = 92+8=100

* p = PDIV+2 = 1+2 = 3

* s = SDIV = 1

* FCLK = 2*m*Fin/(p*2^s) = 2*100*12/(3*2^1)=400M

*/

ldr r0, =0x4C000004

ldr r1, =(92<<12)|(1<<4)|(1<<0)

str r1, [r0]

/* Once the PLL is set, the lock time will be locked until the PLL output is stable

* Then the CPU operates at the new frequency FCLK

*/

/* Set up memory: sp stack */

/* Distinguish whether it is NOR/NAND startup

* Write 0 to address 0, then read it out

* If you get 0, it means the content at address 0 has been modified, it corresponds to ram, this is nand boot

* Otherwise, it is NOR start

*/

mov r1, #0

ldr r0, [r1] /* read out the original value backup */

str r1, [r1] /* 0->[0] */ 

ldr r2, [r1] /* r2=[0] */

cmp r1, r2 /* r1==r2? If they are equal, it means NAND boot*/

ldr sp, =0x40000000+4096 /* Assume that it is NOR startup*/

moveq sp, #4096 /* nand start */

streq r0, [r1] /* restore the original value */

bl main

halt:

b halt