Exynos4412 bare metal development - UART

1. Features of Exynos4412 UART

The UART in Exynos4412 has 4 independent channels, each of which can work in interrupt mode or DMA mode, that is, the UART can issue an interrupt or DMA request to transfer data between the UART and the CPU. The UART consists of a baud rate generator, a transmitter, a receiver, and control logic.

When using the system clock, the UART baud rate of Exynos4412 can reach 4Mbps. The baud rate can be programmed.

The Exynos4412 UART channel 0 has a 256-byte transmit FIFO and a 256-byte receive FIFO; channels 1 and 4 have a 64-byte transmit FIFO and a 64-byte receive FIFO; channels 2 and 3 have a 16-byte transmit FIFO and a 16-byte receive FIFO. When sending data, the CPU first writes the data into the transmit FIFO, and then the UART automatically copies the data in the FIFO to the "transmit shifter", which sends the data one bit at a time to the TxDn data line (inserting the start bit, check bit, and stop bit according to the set format). When receiving data, the "shifter" receives the data on the RxDn data line one bit at a time, and then copies it to the FIFO, from which the CPU can read the data.

Each channel of Exynos4412 UART supports 1 or 2 stop bits, 5, 6, 7 or 8 data bits, supports parity function, and also has infrared sending/receiving function.

Exynos4412 UART block diagram:

2. uart initialization steps:

1. Set the UART channel pins involved to UART function.

For example, in UART channel 0, GPA0_0 and GPA0_1 are used as RXD0 and TXD0 respectively. To use UART channel 0, first set the GPA0CON register to set the functions of GPA0_0 and GPA0_1 pins to RXD0 and TXD0.

2. Select the UART clock source

There are eight clock source options for Exynos4412 UART: XXTI, XusbXTI, SCLK_HDMI24M, SCLK_USBPHY0, SCLK_HDMIPHY, SCLKMPLL_USER_T, SCLKEPLL, SCLKVPLL, controlled by the CLK_SRC_PERIL0 register.

After selecting the clock source, you can also set the division coefficient through DIVUART0 ~ 4, which is controlled by the CLK_DIV_PERIL0 register. The clock obtained from the divider is called SCLK UART.

SCLK UART passes through the "UCLK Generator" in the figure above to get UCLK, whose frequency is the baud rate of the UART. The "Generator UCLK Generator" is set through these two registers: UBRDEVn, UFRACVALn (described below).

3. Set the baud rate: UBRDIVn register (UART BAUD RATE DIVISOR), UFRACVALn register

According to the given baud rate and the selected clock source frequency, the value of the UBRDIVn register (n is 0 to 4, corresponding to 5 UART channels) can be calculated by the following formula.

 UBRDIVn = (int)( UART clock / ( buad rate x 16) ) – 1

The UBRDIVn register value calculated by the above formula is not necessarily an integer. The UBRDIVn register takes the integer part, and the smaller part is set by the UFRACVALn register. The introduction of the UFRACVALn register makes the baud rate more accurate.

For example, when the UART clock is 100MHz, the baud rate is required to be 115200 bps, then:

100000000/(115200 x 16) – 1 = 54.25 – 1 = 53.25

UBRDIVn = integer part = 53

UFRACVALn/16 = fractional part = 0.25

UFRACVALn = 4

4. Set the transmission format: ULCONn register (UART LINE CONTROL)

The format of the ULCONn register (n is 0 to 4) is shown in the figure below:

5. Set UART working mode: UCONn register (UART CONTROL)

6. UFCONn register (UART FIFO CONTROL), UFSTATn register (UART FIFO STATUS)

The UFCON n register is used to set whether to use FIFO and set the trigger threshold of each FIFO, that is, how much data in the send FIFO generates an interrupt, how much data in the receive FIFO generates an interrupt. And each FIFO can be reset by setting the UFCON n register.

By reading the UFSTAT n register, you can know whether each FIFO is full and how much data is in it.

When FIFO is not used, the FIFO depth can be considered to be 1. When FIFO is used, the FIFO depth of Exynos4412 can reach up to 256.

7. UMCONn register (UART MODEM CONTROL), UMSTATn register (UART MODEM STATUS)

These two types of registers are used for flow control and are not introduced here.

8. UTRSTATn Register (UART TX/RX STATUS)

The UTRSTAT n register is used to indicate whether the data has been sent or received. The format is shown in the following table. The "buffer" mentioned below is actually the FIFO in the figure below. When the FIFO function is not used, its depth can be considered to be 1.

9. UERSTATn Register (UART ERROR STATUS)

Used to indicate whether various errors have occurred. When bits [0] to [3] are 1, they indicate overflow error, check error, frame error, and detection of a "break" signal. When this register is read, it is automatically cleared to 0.

It should be noted that if FIFO is used when receiving data, an "error FIFO" will be used inside the UART to indicate which data in the receiving FIFO has an error during the receiving process. The CPU will only be aware of the error when reading the erroneous data. To clear the "FIFO", the erroneous data must be read out and the UERSTATn register must be read out.

10. UTXHn register (UART TRANSMIT BUFFER REGISTER)

The CPU writes data to this register, and the UART saves it in the buffer and sends it out automatically.

11. URXHn register (UART RECEIVE BUFFER REGISTER)

When UART receives data, it reads this register to get the data.

3. Sample Program Writing

The following is a small demo that implements the echo function on the terminal and turns the buzzer on and off by entering "beep_on" and "beep_off" on the terminal:

Header file definition:

1. /*****************************************    UART  * *************************************/  

2. /* UART0*/  

3. typedef struct {  

4.                 unsigned int ULCON0;  

5.                 unsigned int UCON0;  

6.                 unsigned int UFCON0;  

7.                 unsigned int UMCON0;  

8.                 unsigned int UTRSTAT0;  

9.                 unsigned int UERSTAT0;  

10.                 unsigned int UFSTAT0;  

11.                 unsigned int UMSTAT0;  

12.                 unsigned int UTXH0;  

13.                 unsigned int URXH0;  

14.                 unsigned int UBRDIV0;  

15.                 unsigned int UFRACVAL0;  

16.                 unsigned int UINTP0;  

17.                 unsigned int UINTSP0;  

18.                 unsigned int UINTM0;  

19. }uart0;  

20. #define UART0 ( * (volatile uart0 *)0x13800000 )  

UART.c

1. #include "exynos_4412.h"  

2. #include "pwm.h"  

3.   

4. void mydelay_ms(int time)  

5. {  

6.     int i, j;  

7.     while(time--)  

8.     {  

9.         for (i = 0; i < 5; i++)  

10.             for (j = 0; j < 514; j++);  

11.     }  

12. }  

13.   

14. int strcmp(const char *src, const char *des)  

15. {  

16.     while(*src || *des)  

17.     {  

18.         if(*src > *des)  

19.             return 1;  

20.         else if(*src < *des)  

21.             return -1;  

22.         else  

23.         {  

24.             src++;  

25.             des++;  

26.         }  

27.     }  

28.     return 0;  

29. }  

30.   

31. void uart0_init()  

32. {  

33.   

34.     /*UART0 initialize*/  

35.     GPA0.CON = (GPA0.CON & ~0xFF ) | (0x22); //GPA1_0:RX;GPA1_1:TX  

36.   

37.     UART0.ULCON0 = 0x3; //Normal mode, No parity,One stop bit,8 data bits  

38.     UART0.UCON0 = 0x5;  //Interrupt request or polling mode  

39.     //Baud-rate : src_clock:100Mhz  

40.     UART0.UBRDIV0 = 53;  

41.     UART0.UFRACVAL0 = 0x4;  

42. }  

43.   

44. void putc0(const char data)  

45. {  

46.     while(!(UART0.UTRSTAT0 & 0X2));  

47.     UART0.UTXH0 = data;  

48.     if (data == 'n')  

49.             putc0('r');  

50. }  

51. char getc0(void)  

52. {  

53.     char data;  

54.     while(!(UART0.UTRSTAT0 & 0x1));  

55.     data = UART0.URXH0;  

56.     if ((data == 'n') || (data == 'r'))  

57.     {  

58.         putc0('n');  

59.         putc0('r');  

60.     }  

61.     else  

62.         putc0(data);  

63.   

64.     return data;  

65. }  

66. void puts0(const  char  *pstr)  

67. {  

68.     while(*pstr != '')  

69.         putc0(*pstr++);  

70. }  

71.   

72. void gets0(char *p)  

73. {  

74.     char data;  

75.     while((data = getc0())!= 'r')  

76.         *p++ = data;  

77.     if(data == 'r')  

78.         *p++ = 'r';  

79.     *p = '';  

80. }  

81.   

82.   

83. /* 

84.  * Bare metal code, different from the LINUX application layer, must add loop control 

85.  */  

86. int main (void)  

87. {  

88.     char ch[20];  

89.     pwm_init();  

90.     uart0_init();  

91.     char *q = "hello UART!";  

92.     puts0(q);  

93.     while(1)  

94.     {  

95.         gets0(ch);  

96.         puts0(ch);  

97.         if(!strcmp(ch, "beep_onn"))  

98.             beep_on();  

99.         if(!strcmp(ch, "beep_offn"))  

100.             beep_off();  

101.   

102.     //  putc0(getc0());  

103.     }  

104.    return 0;  

105. }  

106.