Exynos4412 bare metal development - watchdog timer

1. Overview of Watchdog Timer

The purpose of the watchdog timer and PWM timing function is different. Its characteristics are that it requires different receiving signals (some external watchdog chips) or resetting the counter to keep the count value not 0. Once no signal is received for some time, or the count value is 0, the watchdog will send a reset signal to reset the system or generate an interrupt.

The function of the watchdog is to reset the system within a certain time interval after the microprocessor enters an error state due to interference. Therefore, the watchdog is an effective measure to ensure the long-term, reliable and stable operation of the system. Currently, most embedded chips have integrated watchdog timers to improve the reliability of system operation.

The watchdog of the 4412 processor is used to reset the processor when the system is disturbed by a fault. It can also be used as a general 16-bit timer to request an interrupt operation. The watchdog timer generates a reset signal of 128 PCLK cycles. The main features are as follows.

1) General purpose interrupt mode 16-bit timer.

2) When the counter is reduced to 0 (overflow occurs), a reset signal of 128 PCLK cycles is generated.

The functional block diagram of the watchdog timer is as follows:

The watchdog module includes a pre-scale factor amplifier, a divide-by-four frequency divider, and a 16-bit counter. The watchdog clock signal source comes from PCLK. In order to obtain a wide range of watchdog signals, PCLK is first pre-scaled and then divided by the divider. The pre-scale factor and the divider value can be determined by the watchdog control register (WTCON). The pre-scale factor ranges from 0 to 255, and the divider ratio can be 16, 32, 64, or 128. The calculation of the watchdog timer clock period is as follows:

Where Prescaler value is the value of the prescaler amplifier; Divison_factor is the divide-by-four ratio, which can be 16, 32, 64, or 128.

Once the watchdog timer is enabled, the value of the watchdog timer data register (WTDAT) cannot be automatically loaded into the watchdog timer (WTCNT). Therefore, an initial value must be written to the watchdog counter (WTCNT) before the watchdog is started. When the 4412 is debugged with embedded ICE, the reset function of the watchdog timer is not enabled. The watchdog timer can determine whether the current CPU is in the debug state from the CPU core signal. If the watchdog timer determines that the current mode is the debug mode, even if the watchdog generates an overflow signal, it still does not generate a reset signal.

2. Watchdog timer related timers

1. Watchdog timer control register (WTCON)

The contents of the WTCON register include: whether the user starts the watchdog timer, the selection of 4 frequency division ratios, whether interrupts are allowed, whether reset operations are allowed, etc.

If the user wants to use the watchdog timer as a general timer, the interrupt should be enabled and the watchdog timer reset should be disabled.

WTCON is described as follows:

2. Watchdog Timer Data Register (WTDAT)

WTDAT is used to specify the timeout period. After the watchdog disables the reset function and turns on the interrupt enable, the watchdog timer is now a normal timer and is used in the same way as a normal timer. When the reset function is used, the system will reset when the value of WTCNT decreases to 0, so the value of WTCNT cannot be loaded into the watchdog count register (WTCNT). The initial value after reset is 0x8000. WTDAT is described as follows:

3. Watchdog count register (WTCNT)

WTCNT contains the current count value of the counter when the watchdog timer is working. WTCNT is described as follows:

3. Programming of Watchdog Timer

1. Watchdog software programming process

Because the watchdog is an operation to reset or interrupt the system, no peripheral hardware circuit is required. To realize the watchdog function, you only need to operate the watchdog register group, that is, the watchdog control register (WTCON), watchdog data register (WTDAT), and watchdog count register (WTCNT).

The general process is as follows:

1) Set the watchdog interrupt operation, including global interrupt and watchdog interrupt enable and definition of watchdog interrupt vector. If only reset operation is performed, this step does not need to be set.

2) Setting of the watchdog control register (WTCON), including setting the pre-division ratio factor, the division value of the divider, interrupt enable and reset enable, etc.

3) Setting of the watchdog data register (WTDAT) and the watchdog count register (WTCNT).

4) Start the watchdog timer.

2. The specific code is as follows:

1. #include "exynos_4412.h"  

2. #include "led.h"  

3. #include "pwm.h"  

4.   

5. void mydelay_ms(int time)  

6. {  

7.     int i, j;  

8.     while(time--)  

9.     {  

10.         for (i = 0; i < 5; i++)  

11.             for (j = 0; j < 514; j++);  

12.     }  

13. }  

14. //*(volatile unsigned int *)(0x11000c20) = 0;  

15. /*  

16.  * Bare metal code, different from the LINUX application layer, must add loop control  

17.  */  

18. void do_irq(void)  

19. {  

20.     static int a = 1;  

21.     int irq_num;  

22.     irq_num = CPU0.ICCIAR&0x3ff; //Get the interrupt number  

23.     switch(irq_num)  

24.     {  

25.     case 57:  

26.         printf("in the irq_handlern");  

27.             EXT_INT41_PEND = EXT_INT41_PEND |((0x1 << 1)); // Clear GPIO interrupt flag  

28.             ICDICPR.ICDICPR1 = ICDICPR.ICDICPR1 | (0x1 << 25); // Clear GIC interrupt flag  

29.         break;  

30.     case 75:  

31.             printf("in the WDT interrupt!n");  

32.             WDT.WTCLRINT = 0;  

33.             ICDICPR.ICDICPR2 = ICDICPR.ICDICPR2 | (0x1 << 11); // Clear GIC interrupt flag  

34.             break;  

35.     }  

36.     CPU0.ICCEOIR = CPU0.ICCEOIR&(~(0x3ff))|irq_num; //Clear CPU interrupt flag  

37. }  

38. void wdt_init(void)  

39. {  

40.     WDT.WTCON = (249 << 8) | (1 << 5) | (1 << 2)|(1 << 0);  

41.     WDT.WTDAT = 25000;  

42.     ICDDCR = 1; // Enable the distributor  

43.     ICDISER.ICDISER2 = ICDISER.ICDISER2 | (0x1 << 11); // Enable the corresponding interrupt to the distributor  

44.     ICDIPTR.ICDIPTR18 = ICDIPTR.ICDIPTR18 & (~(0xff << 24))|(0x1 << 24); //Select CPU interface  

45.     CPU0.ICCPMR = 255; //Interrupt mask priority  

46.     CPU0.ICCICR = 1; // Enable interrupt to CPU  

47. }  

48.   

49.   

50. int main (void)  

51. {  

52.     wdt_init();  

53.     printf("hello reset!n");  

54.     while(1)  

55.     {  

56.         WDT.WTCNT = 25000;  

57.         mydelay_ms(100);  

58.     }  

59.    return 0;  

60. }