ATmega128 reset and interrupt handling

AVR has different interrupt sources. Each interrupt and reset has a separate interrupt vector in the program space. All interrupt events have their own enable bit. When the enable bit is set and the global interrupt enable bit I in the status register is also set, an interrupt can occur. Depending on the value of the program counter PC, interrupts may be automatically disabled when the boot lock bit BLB02 or BLB12 is programmed. This feature improves software security. For details, please refer to P 267 "Memory Programming".

The lowest address of the program memory space is defined by default as the reset and interrupt vectors. For a complete list of vectors, see P 55 "Interrupts". The list also determines the priority of the different interrupts. The lower the address of the vector, the higher the priority. RESET has the highest priority, and the next is INT0 - External Interrupt Request 0. By setting IVSEL in the MCU Control Register (MCUCR), the interrupt vector can be moved to the beginning of the boot Flash. Detailed description is given in P 55 "Interrupts". Programming the fuse bit BOOTRST can also move the reset vector to the beginning of the boot Flash. For details, see P 255 "Supporting Boot Loaders - Self-Programming Capability that Can Read While Writing (RWW, Read-While-Write)".

When an interrupt occurs, the global interrupt enable bit I is cleared and all interrupts are disabled. User software can enable interrupt nesting by setting bit I. At this time, all interrupts can interrupt the current interrupt. I is automatically set after executing the RETI instruction.

Basically there are two types of interrupts. The first is triggered by an event and sets the interrupt flag. For these interrupts, the program counter jumps to the actual interrupt vector to execute the interrupt handling routine, and the hardware will clear the corresponding interrupt flag. The interrupt flag can also be cleared by writing "1" to it. When an interrupt occurs, if the corresponding interrupt enable bit is "0", the interrupt flag is set and remains set until the interrupt is executed or cleared by software. Similarly, if the global interrupt flag is cleared, all interrupts that have occurred will not be executed until I is set. The pending interrupts are then executed in order of interrupt priority.

The second type of interrupt is always triggered as long as the interrupt condition is met. These interrupts do not require an interrupt flag. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

After exiting an interrupt, the AVR always returns to the main program and executes one instruction before it can execute other suspended interrupts.

The status register is not automatically saved when entering the interrupt routine, nor is it automatically restored when the interrupt returns. These tasks must be completed by software.

When you use the CLI instruction to disable interrupts, interrupts are disabled immediately. No interrupt can occur after executing the CLI instruction, even if it occurs while executing CLI. The following example shows how to use this instruction to prevent interrupts from occurring when writing to the EEPROM.

When interrupts are enabled using the SEI instruction, the first instruction that follows is executed before any interrupts are executed.

Interrupt response time

The AVR interrupt response time is at least 4 clock cycles. After 4 clock cycles, the program jumps to the actual interrupt handling routine. During these 4 clock cycles, the PC is automatically pushed to the stack. Under normal circumstances, the interrupt vector is a jump instruction, and this jump takes 3 clock cycles. If the interrupt occurs during the execution of a multi-cycle instruction, the MCU will not execute the interrupt program until the multi-cycle instruction is executed. If the MCU is in sleep mode when the interrupt occurs, the interrupt response time increases to 8 clock cycles. The additional clock cycle is introduced due to the wake-up startup time.

The interrupt return requires 4 clocks, during which the PC (two bytes) will be popped off the stack, the stack pointer will be incremented by two, and the I bit of the status register SREG will be set.