Detailed explanation of the boot method of i.MX6ULL on Linux ARM (IMX6U) bare metal

1. Startup method selection

The BOOT process occurs after the I.MX6U chip is powered on. The chip will select the BOOT mode according to the setting of BOOT_MODE[1:0]. The value of BOOT_MODE[1:0] can be changed in two ways, one is to rewrite eFUSE (fuse), and the other is to modify the corresponding GPIO high and low levels. The first method of modifying eFUSE can only be modified once, and it cannot be modified again, so we do not use it. We use the method of selecting the boot mode by modifying the GPIO high and low levels corresponding to BOOT_MODE[1:0]. All development boards use this method. I.MX6U has a BOOT_MODE1 pin and a BOOT_MODE0 pin. These two pins correspond to BOOT_MODE[1:0]. The schematic diagram of these two pins of the I.MX6U-ALPHA development board is shown in the figure

BOOT_MODE1 and BOOT_MODE0 have 100KΩ pull-down resistors inside the chip, so the default value is 0. We also connected the two pins of BOOT_MODE1 and BOOT_MODE0 to the dip switches on the baseboard, so that we can control the high and low levels of BOOT_MODE1 and BOOT_MODE0 through the dip switches. Taking BOOT_MODE1 as an example, when we turn the first switch of BOOT_CFG to "ON", it is equivalent to the BOOT_MODE1 pin being connected to the 3.3V power supply through the 10K resistor R88. The BOOT_MODE1 inside the chip is also grounded by a 100K pull-down resistor. Therefore, the voltage of BOOT_MODE1 at this time is 100/(10+100)*3.3V= 3V, which is a high level. Therefore, when the 8 switches in BOOT_CFG are turned to "ON", it is a high level, and when they are turned to "OFF", it is a low level.

The I.MX6U has four BOOT modes, which are controlled by BOOT_MODE[1:0], that is, the two IOs BOOT_MODE1 and BOOT_MODE0. The BOOT mode configuration is shown in the table:

①.Serial download

When BOOT_MODE1 is 0 and BOOT_MODE0 is 1, this mode is enabled. Serial download means that the code can be downloaded to the external storage device on the board through USB or UART. We can use the USB port OTG1 to download the code to the SD/EMMC, NAND and other storage devices on the development board. We need to turn BOOT_MODE1 to "OFF" and turn BOOT_MODE0 to "ON". This download requires a software provided by NXP, which is generally used to burn the code to the external storage device in the final mass production.

②. Internal BOOT mode

This mode is enabled when BOOT_MODE1 is 1 and BOOT_MODE0 is 0. In this mode, the chip will execute the internal boot ROM code. This boot ROM code will perform hardware initialization (part of the peripherals), and then copy the code from the boot device (the device where the code is stored, such as SD/EMMC, NAND) to the specified RAM, usually DDR.

2. BOOT ROM initialization content

When we set the BOOT mode to "internal BOOT mode", the boot ROM code inside the I.MX6U will be executed. What will this boot ROM code do? First of all, it must initialize the clock. The system clock set by the boot ROM is shown in the figure.

BT_FREQ mode is 0. You can see that the boot ROM will set the core clock of I.MX6U to 396MHz, that is, the main frequency is 396Mhz. System PLL=528Mhz, USB PLL=480MHz, AHB=132MHz, IPG=66MHz.

The internal boot ROM will turn on the MMU and Cache to speed up execution. The L1 ICache will be turned on when downloading the image, and the L1 DCache, L2 Cache and MMU will be turned on when verifying the image. Once the image verification is completed, the boot ROM will turn off the L1 DCache, L2 Cache and MMU.

The interrupt vector offset will be set to the start position of the boot ROM. When the boot ROM starts the user code, the interrupt vector offset can be reset. Generally, it is reset to the start of our user code.

3. Select the boot device

When BOOT_MODE is set to internal BOOT mode, you can boot from the following devices:

①. 16-bit NOR Flash connected to CS0 of EIM interface.

②. OneNAND Flash connected to CS0 of EIM interface.

③. MLC/SLC NAND Flash connected to the GPMI interface. NAND Flash page size supports 2KByte, 4KByte and 8KByte, 8-bit width.

④. Quad SPI Flash.

⑤. SD/MMC/eSD/SDXC/eMMC and other devices connected to the USDHC interface.

⑥. EEPROM with SPI interface.

How to select these boot devices? I.MX6U also provides two configuration methods: eFUSE and GPIO. eFUSE will not be explained here. We will focus on how to select the boot device through GPIO, because all I.MX6U development boards configure the boot device through GPIO. Just as the boot mode is selected by BOOT_MODE[1:0], the boot device is configured through 24 configuration IOs, BOOT_CFG1[7:0], BOOT_CFG2[7:0], and BOOT_CFG4[7:0]. These 24 configuration IOs just correspond to the 24 data lines of the LCD, LCD_DATA0~LCDDATA23. After the boot is completed, these 24 IOs can be used as the data lines of the LCD. These 24 lines and BOOT_MODE1 and BOOT_MODE0 together constitute the boot selection pins of I.MX6U, as shown in the figure.

Although there are 24 IOs, only a few IOs need to be adjusted. All other IOs can be pulled down to ground, that is, set to 0. Open the core board schematic of the I.MX6U-ALPHA development board, the default settings of these 24 IOs are shown in the figure

Most of the IOs are grounded, only a few are connected high, especially the 8 IOs BOOT_CFG4[7:0] are pulled down to ground by 10K resistors, so we don’t need to pay attention to BOOT_CFG4[7:0]. The only 16 IOs we need to focus on are BOOT_CFG2[7:0] and BOOT_CFG1[7:0]. The meaning of these 16 configuration IOs is posted on the left side of the schematic, as shown in the figure

Open the baseboard schematic of the I.MX6U-ALPHA development board. The schematic diagram of the boot device selection dip switch on the baseboard is shown in the figure

In addition to BOOT_MODE1 and BOOT_MODE0, LCD_DATA3~LCDDATA7, LCD_DATA11 and other 6 IOs are also brought out. The corresponding high and low levels can be set by the dip switch. When the dip switch is turned to "ON", it is 1, and when it is turned to "OFF", it is 0. Among them, LCD_DATA11 is BOOT_CFG2[3], LCD_DATA3~LCD_DATA7 are BOOT_CFG1[3]~BOOT_CFG1[7]. The configuration meaning of these 6 IOs is shown in the table.

BOOT IO meaning, when the I.MX6U-ALPHA development board boots from SD card, EMMC, NAND, the settings of the DIP switches are as shown in the table