Figure 5 illustrates the concept of parallel instruction fetching and execution determined by the Harvard architecture, as well as the register file that can be accessed quickly. This is a basic pipeline concept with performance up to 1 MIPS/MHz, and excellent price/performance, function/clock ratio, and function/power ratio.
Figure 6 shows the internal access timing of the register file. In one clock cycle, the ALU can operate on two register operands at the same time and save the result to the destination register.
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