Linux ARM (IMX6U) bare metal main frequency and clock configuration

The standard operating frequency of the I.MX6U series is 528MHz, and some models can even work up to 696MHz, but the default operating frequency is 396MHz, which is a waste. This time we will configure the main clock to work at 528MHz, and other peripheral clock sources to work at the operating frequency recommended by NXP.

1. Detailed explanation of I.MX6U clock system

The system main frequency of I.MX6U is 528MHz, and some models can run up to 696MHz, but by default the internal boot rom will set the main frequency of I.MX6U to 396MHz. When we use I.MX6U, we must give full play to its maximum performance, so the main frequency must be set to 528MHz (other models can be set higher, such as 696MHz), and other peripheral clocks must also be set to the values ​​recommended by NXP. Please refer to the NXP official reference manual.

1.1 System clock source

Open the I.MX6U-ALPHA development board schematic diagram. The development board clock schematic diagram is as shown below:

The system clock of I.MX6U-ALPHA development board comes from two parts: 32.768KHz and 24MHz crystal oscillators. The 32.768KHz crystal oscillator is the RTC clock source of I.MX6U, and the 24MHz crystal oscillator is the clock source of I.MX6U core and other peripherals.

1.2、7-channel PLL clock source

I.MX6U has many peripherals, and different peripherals have different clock sources. NXP has grouped the clock sources of these peripherals into 7 groups. These 7 groups of clock sources are all from 24MHz crystal oscillator PLL, so they are also called 7 groups of PLL. The structure of these 7 groups of PLL is shown in the figure:

1.3. Specific functions of 7-channel PLL

1.4. Introduction to Clock Tree

All peripheral clock sources of I.MX6U come from these 7 PLLs and PFDs of some PLLs. How do these peripherals select PLL or PFD? This requires the help of the clock tree in the "IMX6ULL Reference Manual". Section 18.3 of "Chapter 18 Clock Controller Module (CCM)" gives a detailed clock tree diagram of I.MX6U, as shown in the figure:

There are three parts in the figure: CLOCK_SWITCHER, CLOCK ROOT GENERATOR and

SYSTEM CLOCKS. The CLOCK_SWITCHER on the left is the 7-way PLL and 8-way PFD, the SYSTEM CLOCKS on the right is the chip peripherals, and the CLOCK ROOT GENERATOR in the middle is the most complicated! This part is like a "matchmaker", connecting the CLOCK_SWITCHER on the left and the SYSTEM CLOCKS on the right. There are multiple peripheral clock sources to choose from, and the CLOCK ROOT GENERATOR is responsible for selecting the appropriate clock source from the 7-way PLL and 8-way PFD for the peripherals to use. The specific operation is definitely to set the corresponding registers. Let's take the ESAI peripheral as an example. The clock diagram of ESAI is as follows:

In the figure we have divided it into 3 parts, which are as follows:

①. This part is the clock source selector. ESAI has 4 optional clock sources: PLL4, PLL5, PLL3_PFD2 and pll3_sw_clk. The specific selection of which channel as the ESAI clock source is determined by the ESAI_CLK_SEL bit of the register CCM->CSCMR2. The user can configure it freely. The configuration is shown in the figure:

② This part is the pre-division of the ESAI clock. The division value is determined by the ESAI_CLK_PRED of the register CCM_CS1CDR. It can be set to 1~8 division. If PLL4=650MHz now, we choose PLL4 as the ESAI clock, and the pre-division chooses 2 division, then the clock at this time is 650/2=325MHz.

③. This part is a frequency divider, which further divides the clock output in ②. The frequency division value is determined by the ESAI_CLK_PODF of the register CCM_CS1CDR, which can be set to 1~8. If we set it to 8, the clock after this frequency divider is 325/8=40.625MHz. Therefore, the clock that finally enters the ESAI peripheral is 40.625MHz.

Other peripherals are basically similar

1.5. Core clock settings

The clock system of I.MX6U has been analyzed almost completely, and now we can start to set the corresponding clock frequency. Let's start with the main frequency. We set the main frequency of I.MX6U to 528MHz. According to the clock tree, we can see the ARM core clock as shown in the figure:

The details of each part in the figure are as follows:

①. The core clock source comes from PLL1. Suppose PLL1 is 996MHz at this time.

②. PLL1 is divided by the ARM_PODF bit of register CCM_CACRR. You can choose 1/2/4/8 division. If we choose 2 division, the clock frequency after division is 996/2=498MHz.

③. Don’t be fooled by the 2-way frequency division here. There is no 2-way frequency division here (I was fooled by this 2-way frequency division for a long time.

The main frequency has been configured incorrectly! ).

④. After the frequency division by 2 in step ②, the 498MHz is the core clock of ARM, which is also the main frequency of I.MX6U.

After analyzing the above steps, we know that if we want to set the core frequency to 528MHz, then PLL1 can be set to 1056MHz, and the ARM_PODF bit of register CCM_CACRR can be set to 2 division. Similarly, if the main frequency is set to 696MHz, then PLL1 can be set to 696MHz, and the ARM_PODF of CCM_CACRR can be set to 1 division. Now the problem is very clear, the ARM_PODF bit of register CCM_CACCR is easy to set, and the frequency of PLL1 can be set through register CCM_ANALOG_PLL_ARMn. Next, take a closer look at the two registers CCM_CACRR and CCM_ANALOG_PLL_ARMn. The CCM_CACRR register structure is shown in the figure:

The register CCM_CACRR only has the ARM_PODF bit, which can be set to 0~7, corresponding to frequency divisions of 1 to 8. If you want to set the frequency division to 2, CCM_CACCR must be set to 1.

Let's take a look at the register CCM_ANALOG_PLL_ARMn. The register structure is shown in the figure:

The important bits in register CCM_ANALOG_PLL_ARMn are as follows:

When modifying the PLL1 clock frequency, we need to first change the core clock source to another clock source. The selectable clock sources for PLL1 are shown in the figure:

①. pll1_sw_clk is the final output frequency of PLL1.

②. This is a selector, which selects the clock source of pll1_sw_clk. The PLL1_SW_CLK_SEL bit of register CCM_CCSR determines whether pll1_sw_clk selects pll1_main_clk or step_clk. Under normal circumstances, pll1_main_clk should be selected, but if the frequency of pll1_main_clk (PLL1) needs to be adjusted, for example, if we want to set PLL1=1056MHz, we need to switch pll1_sw_clk to step_clk first. Switch back after the adjustment of pll1_main_clk is completed.

③. This is also a selector, which selects the clock source of step_clk. The STEP_SEL bit of the register CCM_CCSR determines whether step_clk selects osc_clk or secondary_clk. Generally, osc_clk is selected, which is a 24MHz crystal oscillator. Here we use a register CCM_CCSR, and the register structure is shown in the figure:

Register CCM_CCSR We only use two bits, STEP_SEL and PLL1_SW_CLK_SEL, one is used to select the step_clk clock source, and the other is used to select the pll1_sw_clk clock source.

At this point, the steps to modify the main frequency of I.MX6U are very clear. The modification steps are as follows:

①. Set the STEP_SEL bit of the CCSR register and set the clock source of step_clk to a 24M crystal oscillator.

②. Set the PLL1_SW_CLK_SEL bit of the CCSR register, and set the clock source of pll1_sw_clk to step_clk=24MHz. Through this step, we set the main frequency of I.MX6U to 24MHz, which comes directly from the external 24M crystal oscillator.

③、Set register CCM_ANALOG_PLL_ARMn and set pll1_main_clk(PLL1) to 1056MHz.

④. Set the PLL1_SW_CLK_SEL bit of the CCSR register to switch the clock source of pll1_sw_clk back to pll1_main_clk. After switching back, the pll1_sw_clk is equal to 1056MHz.

⑤. Finally, set the ARM_PODF of register CCM_CACRR to 2 division, and the core frequency of I.MX6U is 1056/2=528MHz.

1.6. PFD clock setting

After setting the main frequency, we also need to set other PLL and PFD clocks. PLL1 has been set, PLL2, PLL3 and PLL7 are fixed to 528MHz, 480MHz and 480MHz, PLL4~PLL6 are for special peripherals and will be set when used. Therefore, the next focus is to set the 4 PFDs of PLL2 and PLL3 respectively. The 8 PFD frequencies recommended by NXP are shown in the table:

First, set the 4-channel PFD frequency of PLL2. The register used is CCM_ANALOG_PFD_528n. The register structure is shown in the figure:

As can be seen from the figure, the register CCM_ANALOG_PFD_528n is actually divided into four groups, corresponding to PFD0~PFD3, each group has 8 bits. Let's take PFD0 as an example to see how to set the frequency of PLL2_PFD0. The register bits corresponding to PFD0 are as follows:

If we want to set the frequency of PLL2_PFD0 to 352MHz, we need to set PFD0_FRAC to 27 and PFD0_CLKGATE to 0. PLL2_PFD1~PLL2_PFD3 settings are similar, and the frequency calculation formula is 528*18/PFDX_FRAC (X=1~3), so if PLL2_PFD1=594MHz, PFD1_FRAC=16; if PLL2_PFD2=400MHz, PFD2_FRAC cannot be divided evenly, so take the nearest integer value, that is, PFD2_FRAC=24, so that PLL2_PFD2 is actually 396MHz; if PLL2_PFD3=297MHz, PFD3_FRAC=32.

Next, set the frequencies of the four PFDs PLL3_PFD0~PLL3_PFD3. The register used is CCM_ANALOG_PFD_480n. The register structure is shown in the figure:

As can be seen from the figure, the structures of registers CCM_ANALOG_PFD_480n and CCM_ANALOG_PFD_528n are exactly the same, except that one is for PLL2 and the other is for PLL3. The meaning of the register bits is also the same, but the frequency calculation formula is different, such as PLL3_PFDX=480*18/PFDX_FRAC(X=0~3). If PLL3_PFD0=720MHz, PFD0_FRAC=12; if PLL3_PFD1=540MHz, PFD1_FRAC=16; if PLL3_PFD2=508.2MHz, PFD2_FRAC=17; if PLL3_PFD3=454.7MHz, PFD3_FRAC=19.

1.7、AHB, IPG and PERCLK root clock settings

After the 7-way PLL and 8-way PFD settings are completed, you need to set AHB_CLK_ROOT and IPG_CLK_ROOT

The setting range of I.MX6U peripheral root clock is as shown in the figure:

The figure shows the root clock setting range of most peripherals. AHB_CLK_ROOT can be set up to 132MHz, and IPG_CLK_ROOT and PERCLK_CLK_ROOT can be set up to 66MHz. Then we set AHB_CLK_ROOT, IPG_CLK_ROOT and PERCLK_CLK_ROOT to 132MHz, 66MHz, and 66MHz respectively. The relationship between AHB_CLK_ROOT and IPG_CLK_ROOT is shown in the figure below: