STM8S (105K4) user notes - basic configuration of independent watchdog IWDG

0. Use of independent watchdog

The independent watchdog operates from a low speed internal RC oscillator (LSI).

If the LSI runs normally, when an error occurs in the main program, the watchdog counter cannot be reset, and the independent watchdog will generate a reset flag and restart.

Since the independent watchdog runs based on LSI, it is independent of the main program and most peripherals, which can maximize the normal operation of the independent watchdog function.

1. Enable independent watchdog

  /* Enable independent watchdog (low speed internal RC oscillator (LSI) will be enabled by hardware) */

  IWDG->KR = (uint8_t)0xCC;

NOTE! Once the independent watchdog is enabled it cannot be disabled!

If you need to use the low power mode of stm8s and the watchdog reset function, please select the window watchdog!

2. Configure the frequency division factor and reload value

Remove the write protection of PR and RLR registers

  /* PR and RLR registers are write-protected. Write 0x55 to the KR register to remove the write protection. */

  IWDG->KR = (uint8_t)0x55;

  /* Restore write protection by writing 0xAA. */

  IWDG->KR = (uint8_t)0xAA;

Setting the IWDG crossover

  /* 4-way division*/

  IWDG->PR = (uint8_t)0x00;

  /* 8-way division*/

  IWDG->PR = (uint8_t)0x01;

  /* 16-division*/

  IWDG->PR = (uint8_t)0x02;

  /* 32 frequency division */

  IWDG->PR = (uint8_t)0x03;

  /* 64 division*/

  IWDG->PR = (uint8_t)0x04;

  /* 128 division*/

  IWDG->PR = (uint8_t)0x05;

  /* 256 division*/

  IWDG->PR = (uint8_t)0x06;

Set IWDG auto-reload value

  /* IWDG_Period is the auto-reload value that needs to be set*/

  IWDG->RLR = (uint8_t)(IWDG_Period);

IWDG timing trigger formula

IWDG_Period= (time * IWDG_Counter_Clock - 1);

IWDG_Period is the automatic reload value set

time is the time required for IWDG to trigger (s)

IWDG_Counter_Clock is the IWDG frequency, which is equal to the LSI/IWDG division value (hz)

3. Initialization case

  __IO uint32_t LsiFreq = 128000;

  /* Enable IWDG (the LSI oscillator will be enabled by hardware) */

  IWDG->KR = (uint8_t)0xCC;

  /* IWDG timeout equal to 250 ms (the timeout may varies due to LSI frequency

     dispersion) */

  /* Enable write access to IWDG_PR and IWDG_RLR registers */

  IWDG->KR = (uint8_t)0x55;

  /* IWDG counter clock: LSI(128KHZ)/128 = 1000 */

  IWDG->PR = (uint8_t)0x05;

  /* Set counter reload value to obtain 250ms IWDG Timeout.

    Counter Reload Value = 250ms/IWDG counter clock period

                         = 250ms / (LSI/128)

                         = 0.25s / (LsiFreq/128)

                         = LsiFreq/(128 * 4)

                         = LsiFreq/512

   */

  IWDG->RLR = ((uint8_t)(LsiFreq / 512));

  /* Reload IWDG counter */

  IWDG->KR = (uint8_t)0xAA;

Main function

  void main(void)

  {

    /**

    * omission

    *

    */

    while (1)

    {

      /**

      * omission

      *

      */

  /* Reload IWDG counter */

      IWDG_ReloadCounter();

    }

  }